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hotfix in minor Verilog generation

This commit is contained in:
tangxifan 2019-08-06 11:58:27 -06:00
parent b207050b03
commit afa468a442
1 changed files with 1 additions and 1 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
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@ -2895,7 +2895,7 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) {
fprintf(fp, "begin\n");
fprintf(fp, "\tdata_reg = %d'b0;\n", num_outputs);
fprintf(fp, "\tif ((0 < addr) && (addr < %d) ) begin\n", num_outputs);
fprintf(fp, "\t\tdata_reg = 1'b1 << (addr - 1)\n");
fprintf(fp, "\t\tdata_reg = 1'b1 << (addr - 1);\n");
fprintf(fp, "\tend\n");
fprintf(fp, "end\n");