bug fixing for pb_type num_conf_bits and num_iopads stats

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c

@@ -1023,6 +1023,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,
     cur_pb_type->physical_mode_num_reserved_conf_bits = 
          count_num_reserved_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model,
                                                       cur_sram_orgz_info->type, 0);
+
   } else { /* Count the sum of configuration bits of all the children pb_types */
     /* Find the mode that define_idle_mode*/
     mode_index = find_pb_type_physical_mode_index((*cur_pb_type));
@@ -1232,6 +1233,28 @@ void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) {
   return;
 }
 
+/********************************************************************
+ * Initialize the number of configuration bits for each pb_type
+ * in the list of type descriptors
+ *******************************************************************/
+void init_pb_types_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) {
+  for (int itype = 0; itype < num_types; ++itype) {
+    /* bypass EMPTY_TYPES */
+    if (EMPTY_TYPE == &(type_descriptors[itype])) {
+      continue;
+    }
+    int capacity= type_descriptors[itype].capacity;
+    assert(0 < capacity);
+
+    /* check capacity and if this has been mapped */
+    for (int iz = 0; iz < capacity; iz++) {
+      /* Check in all the blocks(clustered logic block), there is a match x,y,z*/
+      rec_count_num_conf_bits_pb_type_physical_mode(type_descriptors[itype].pb_type, cur_sram_orgz_info);
+    }
+  }
+  return;
+}
+
 /* With given spice_model_port, find the pb_type port with same name and type*/
 t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,
                                                  t_spice_model_port* spice_model_port) {
@@ -1793,6 +1816,29 @@ void init_grids_num_iopads() {
   return;
 }
 
+/********************************************************************
+ * Initialize the number of configuration bits for each pb_type
+ * in the list of type descriptors
+ *******************************************************************/
+void init_pb_types_num_iopads() {
+  for (int itype = 0; itype < num_types; ++itype) {
+    /* bypass EMPTY_TYPES */
+    if (EMPTY_TYPE == &(type_descriptors[itype])) {
+      continue;
+    }
+
+    int capacity= type_descriptors[itype].capacity;
+    assert(0 < capacity);
+
+    /* check capacity and if this has been mapped */
+    for (int iz = 0; iz < capacity; iz++) {
+      /* Check in all the blocks(clustered logic block), there is a match x,y,z*/
+      rec_count_num_iopads_pb_type_physical_mode(type_descriptors[itype].pb_type);
+    }
+  }
+  return;
+}
+
 /* Count the number of mode configuration bits of a grid (type_descriptor) in default mode */
 void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type) {
   int mode_index, ipb, jpb;

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h

@@ -93,6 +93,8 @@ void init_one_grid_num_conf_bits(int ix, int iy,
 
 void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info);
 
+void init_pb_types_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info);
+
 void map_clb_pins_to_pb_graph_pins();
 
 t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,
@@ -135,6 +137,8 @@ void init_one_grid_num_iopads(int ix, int iy);
 
 void init_grids_num_iopads();
 
+void init_pb_types_num_iopads();
+
 void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type);
 
 void rec_count_num_mode_bits_pb(t_pb* cur_pb);

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c

@@ -242,8 +242,10 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
   /* Initialize the number of configuration bits of all the grids */
   vpr_printf(TIO_MESSAGE_INFO, "Count the number of configuration bits, IO pads in each logic block...\n");
   /* init_grids_num_conf_bits(sram_verilog_orgz_type); */
-  init_grids_num_conf_bits(sram_verilog_orgz_info);
-  init_grids_num_iopads();
+  //init_grids_num_conf_bits(sram_verilog_orgz_info);
+  init_pb_types_num_conf_bits(sram_verilog_orgz_info);
+  //init_grids_num_iopads();
+  init_pb_types_num_iopads();
   /* init_grids_num_mode_bits(); */
 
   dump_verilog_defines_preproc(src_dir_path,