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Author SHA1 Message Date
William D. Jones c76f361b56 machxo2: synth_machxo2 now maps ports to FACADE_IO. 2021-02-23 17:39:58 +01:00
William D. Jones 03cbf1327d machxo2: Add initial value for Q in FACADE_FF. 2021-02-23 17:39:58 +01:00
William D. Jones 0364ded385 machxo2: Add FACADE_IO simulation model. More comments on models. 2021-02-23 17:39:58 +01:00
William D. Jones 1b703d3f03 machxo2: Add FACADE_SLICE simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones cc52eb53cd machxo2: Improve FACADE_FF simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones 427fed23ee machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. 2021-02-23 17:39:58 +01:00
William D. Jones 84937e9689 machxo2: Add dff.ys test, fix another cells_map.v typo. 2021-02-23 17:39:58 +01:00
William D. Jones 044393b990 machxo2: Fix more oversights in machxo2 models. logic.ys test passes. 2021-02-23 17:39:58 +01:00
William D. Jones b87f6a0906 machxo2: Fix typos. test/arch/run-test.sh passes. 2021-02-23 17:39:58 +01:00
William D. Jones 88c8f81260 machxo2: Create basic techlibs and synth_machxo2 pass. 2021-02-23 17:39:58 +01:00
gatecat 9f7cd10c98
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct 
nexus: Add MULTADDSUB9X9WIDE sim model
 2021-02-12 12:07:12 +00:00
Zachary Snow fe74b0cd95 verilog: significant block scoping improvements 
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493
 2021-01-31 09:42:09 -05:00
Marcelina Kościelnicka ea79e16bab xilinx_dffopt: Don't crash on missing IS_*_INVERTED. 
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.
 2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka cd6f0732f3 xilinx: Add FDRSE_1, FDCPE_1. 2021-01-27 00:32:00 +01:00
Tom Verbeure 87637e8359 Fix some trivial typos. 2021-01-03 23:52:59 -08:00
whitequark b0d4c63957
Merge pull request #2480 from YosysHQ/dave/nexus-lram 
nexus: Add LRAM inference
 2021-01-01 09:49:00 +00:00
Marcelina Kościelnicka f2932628fc xilinx: Add some missing blackbox cells. 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka 5ffb676fa9 xilinx: Regenerate cells_xtra.v using Vivado 2020.2 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka 871fc34ad4 xilinx: Add FDDRCPE and FDDRRSE blackbox cells. 
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
 2020-12-17 03:25:07 +01:00
David Shah f5cc1224f9 nexus: Add MULTADDSUB9X9WIDE sim model 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-08 15:49:20 +00:00
David Shah 17812a1560 nexus: Add LRAM inference 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 13:27:17 +00:00
David Shah 264e924abb nexus: More efficient CO mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:08:39 +00:00
Pepijn de Vos f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
David Shah 9f241c9a42 nexus: DSP inference support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-20 08:45:55 +00:00
Miodrag Milanović c8d809897f
Merge pull request #2441 from YosysHQ/dave/nexus_dsp_sim 
nexus: Add DSP simulation model
 2020-11-18 12:22:05 +01:00
David Shah 923843b3fa nexus: Add DSP simulation model 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-18 10:21:17 +00:00
Miodrag Milanovic aa4d94f7d8 Fix duplicated parameter name typo 2020-11-18 10:03:57 +01:00
Konrad Beckmann 5b9a975eba synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
David Shah 6d63e58e46 nexus: Add make_transp to BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-22 15:11:59 +01:00
clairexen e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells 
xilinx/cells_sim.v: Move signal declaration to before first use
 2020-10-20 17:11:36 +02:00
Jeff Goeders 8be56960a2 Move signal declarations to before first use 
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
 2020-10-19 16:09:18 -06:00
David Shah 4d584d9319 synth_nexus: Initial implementation 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-15 08:52:15 +01:00
Eddie Hung de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
 2020-09-23 09:15:24 -07:00
Dan Ravensloft 028f96e536 intel_alm: better map wide but shallow multiplies 2020-08-28 23:44:16 +02:00
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
Marcelina Kościelnicka 082cbcb4c7 synth_intel: Remove incomplete Arria 10 GX support. 
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
 2020-08-21 01:46:06 +02:00
Dan Ravensloft 034b9ec716 intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
clairexen d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
 2020-08-20 16:25:56 +02:00
clairexen 1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern 
techmap: Add support for [] wildcards in techmap_celltype.
 2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka 50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path. 
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
 2020-08-20 12:44:09 +02:00
Xiretza 928fd40c2e Respect \A_SIGNED for $shift 
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
 2020-08-18 19:36:24 +02:00
Dan Ravensloft 3b534a203a intel_alm: fix typo in MISTRAL_MUL27X27 cell name 2020-08-13 17:08:50 +02:00
Dan Ravensloft 97daf612cb intel_alm: add more megafunctions. NFC. 2020-08-12 18:39:22 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka 522788f016 techmap: Add support for [] wildcards in techmap_celltype. 
Fixes #1826.
 2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka 6cd135a5eb opt_expr: Remove -clkinv option, make it the default. 
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
 2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka cf60699884 synth_ice40: Use opt_dff. 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka 8501342fc5 synth_xilinx: Use opt_dff. 
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:09 +02:00
Dan Ravensloft a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
 2020-07-27 15:39:06 +02:00
Dan Ravensloft 62311b7ec0 intel_alm: increase abc9 -W 2020-07-26 23:56:54 +02:00
clairexen 02583ad504
Merge pull request #2294 from Ravenslofty/intel_alm_timings 
intel_alm: add additional ABC9 timings
 2020-07-23 18:21:20 +02:00
Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Keith Rothman 819f1d8c20 Remove EXPLICIT_CARRY logic. 
The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-07-23 00:56:09 +02:00
Marcelina Kościelnicka 1b95b0e570 sf2: Emit CLKINT even if -clkbuf not passed 
This restores pre #2229 behavior.
 2020-07-17 15:01:47 +02:00
Miodrag Milanović 10bc0967e2
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix 
anlogic: Fix FF mapping.
 2020-07-17 14:39:31 +02:00
Marcelina Kościelnicka a4f7777e9d anlogic: Fix FF mapping. 2020-07-17 14:03:21 +02:00
clairexen 9a5d6e1789
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs 
sf2: replace sf2_iobs with {clkbuf,iopad}map
 2020-07-16 18:33:56 +02:00
Miodrag Milanović 910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic 
anlogic: Use dfflegalize.
 2020-07-16 18:07:58 +02:00
Miodrag Milanović b74eb598bc
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf 
efinix: Nuke efinix_gbuf in favor of clkbufmap.
 2020-07-16 18:07:41 +02:00
Marcelina Kościelnicka a786091b46 achronix: Use dfflegalize. 2020-07-14 23:12:16 +02:00
Marcelina Kościelnicka 3050454d6e anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
Marcelina Kościelnicka 3209c0762a intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
Lofty a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00
Marcelina Kościelnicka 347dd01c2f xilinx: Fix srl regression. 
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
 2020-07-12 23:41:27 +02:00
Dan Ravensloft 7dc0439de4 sf2: replace sf2_iobs with {clkbuf,iopad}map 2020-07-09 21:28:52 +01:00
Marcelina Kościelnicka edbaf2fdf6 sf2: Use dfflegalize. 2020-07-09 21:56:14 +02:00
Marcelina Kościelnicka f313211c32 xilinx: Use dfflegalize. 2020-07-09 18:54:23 +02:00
Marcelina Kościelnicka d5e5d96527 efinix: Use dfflegalize. 2020-07-06 12:28:17 +02:00
Marcelina Kościelnicka c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Dan Ravensloft 09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft 7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Marcelina Kościelnicka b5f3b70cfe
Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40 
ice40: Use dfflegalize.
 2020-07-05 18:50:25 +02:00
Marcelina Kościelnicka 372521ca56 ecp5: Use dfflegalize. 2020-07-05 18:49:41 +02:00
Marcelina Kościelnicka 90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init 
gowin: Fix INIT values in sim library.
 2020-07-05 12:02:31 +02:00
Dan Ravensloft b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka 1fc8c3a0d1 ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
Marcelina Kościelnicka 9beed4d771 gowin: Fix INIT values in sim library. 2020-07-05 03:03:48 +02:00
Dan Ravensloft 01772dec8c gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
Marcelina Kościelnicka 3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Marcelina Kościelnicka 6b0ac04698 efinix: Nuke efinix_gbuf in favor of clkbufmap. 2020-07-04 20:53:43 +02:00
Dan Ravensloft c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung 2bdced0d68 intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF 2020-07-04 19:45:10 +02:00
Eddie Hung 3db3e1e149 intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
Dan Ravensloft 83cde2d02b intel_alm: ABC9 sequential optimisations 2020-07-04 19:45:10 +02:00
Marcelina Kościelnicka 817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka 832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types 
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
 2020-06-23 15:40:02 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Xark 9509444ef2 Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
Dan Ravensloft 8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 15:54:14 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Eddie Hung 5b81df57c8 xilinx: tidy up cells_sim.v a little 2020-05-25 09:48:11 -07:00
Eddie Hung 76e0cc8276 ecp5: cleanup unused +/ecp5/abc9_model.v 2020-05-23 08:17:40 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 
instead of moving them to $__ prefix
 2020-05-14 16:44:35 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ... 
replacing _all_ (* abc9_box *) instantiations with their derived types
 2020-05-14 10:33:57 -07:00
Eddie Hung e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung cea614f5ae ecp5: latches_map.v if *not* -asyncprld 2020-05-14 10:33:57 -07:00
Eddie Hung fdc340db8e ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v 2020-05-14 10:33:57 -07:00
Eddie Hung 39759d5f0e ecp5: fix rebase mistake 2020-05-14 10:33:57 -07:00
Eddie Hung ca4f8c9444 xilinx: gate specify/attributes from iverilog 2020-05-14 10:33:57 -07:00
Eddie Hung 57c478c537 abc9: only do +/abc9_map if `DFF 2020-05-14 10:33:57 -07:00
Eddie Hung 8cda29137e ecp5: TRELLIS_FF bypass path only in async mode 2020-05-14 10:33:56 -07:00
Eddie Hung 6c34945371 xilinx/ice40/ecp5: zinit requires selected wires, so select them all 2020-05-14 10:33:56 -07:00
Eddie Hung a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 8fbb55f4ab synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung 4cec21b93e abc9_ops: -prep_dff_map to error if async flop found 2020-05-14 10:33:56 -07:00
Eddie Hung 6c66030dfb Uncomment negative setup times; clamp to zero for connectivity 2020-05-14 10:33:56 -07:00
Eddie Hung 0d84ff3fc4 Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" 
This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
 2020-05-14 10:33:56 -07:00
Eddie Hung a52f779eca ecp5: (* abc9_flop *) gated behind YOSYS 2020-05-14 10:33:56 -07:00
Eddie Hung 34c7732642 ecp5: add synth_ecp5 -dff to work with -abc9 2020-05-14 10:33:56 -07:00
Eddie Hung 23c53a6bdd ice40: synth_ice40 cleanup 2020-05-14 10:33:56 -07:00
Eddie Hung 5d5029fa75 ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init 2020-05-14 10:33:56 -07:00
Eddie Hung fe7965e0ee ice40: add synth_ice40 -dff option, support with -abc9 2020-05-14 10:33:56 -07:00
Eddie Hung 4a10c87ae1 ice40: split out cells_map.v into ff_map.v 2020-05-14 10:33:56 -07:00
Eddie Hung c10757a8ea synth_xilinx: rename dff_mode -> dff 2020-05-14 10:33:56 -07:00
Eddie Hung 95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Eddie Hung 27b7ffc754 ice40: fix ICESTORM_LC process sensitivity 2020-05-12 15:40:48 -07:00
Eddie Hung 4ecae8a673 ice40: fix whitespace 2020-05-12 15:40:13 -07:00
David Shah 95fb3cf487 ecp5: Add missing SERDES parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-12 21:12:26 +01:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Eddie Hung 004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Eddie Hung e6b55e8b38 synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad 2020-05-04 11:44:00 -07:00
whitequark 26cda3c247 gowin,ecp5: remove generated files in `make clean`. 2020-04-24 23:26:39 +00:00
Dan Ravensloft 4ca5f9799b intel_alm: cleanup duplication 2020-04-24 11:26:48 +02:00
Dan Ravensloft 3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Eddie Hung 51ae0f4e20 ecp5: ecp5_gsr to skip cells that don't have GSR parameter again 2020-04-22 17:53:08 -07:00
Eddie Hung d2d90e4504 xilinx: improve xilinx_dffopt message 2020-04-22 16:25:23 -07:00
Eddie Hung 7f33a0294b Cleanup use of hard-coded default parameters in light of #1945 2020-04-22 12:02:30 -07:00
Dan Ravensloft 16a3048308 intel_alm: Documentation improvements 2020-04-21 19:38:15 +02:00
Marcelina Kościelnicka b4d76309e1 Use default parameter value in getParam 
Fixes #1822.
 2020-04-21 19:09:00 +02:00
David Shah 1664bcda12 ecp5: Force SIGNED ports to be 1 bit 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 16:38:19 +01:00
Marcelina Kościelnicka 53ba3cf718 Fix the truth table for $_SR_* cells. 
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
 2020-04-15 17:17:48 +02:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Dan Ravensloft 43cc6bd8a1 synth_intel_alm: VQM support 2020-04-15 16:15:25 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
Eddie Hung d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
 2020-04-03 16:28:25 -07:00
Eddie Hung 7b38cde2df cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp 2020-04-03 14:28:22 -07:00
Eddie Hung 7b09a20c0c cmp2lcu: fail if `LUT_WIDTH < 2 2020-04-03 14:28:22 -07:00
Eddie Hung 34c9b83854 synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
Eddie Hung 5b87720b16 synth: use +/cmp2lcu.v in generic 'synth' too 2020-04-03 14:28:22 -07:00
Eddie Hung 2bf03c6ae0 Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
Eddie Hung 051aefc3c2 synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse' 2020-04-03 14:28:22 -07:00
Eddie Hung 99a32432aa +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
Eddie Hung f68d723cdc Refactor +/cmp2lcu.v into recursive techmap 2020-04-03 14:28:22 -07:00
Eddie Hung 8e851badc4 Cleanup 2020-04-03 14:28:22 -07:00
Eddie Hung da880d5016 Cleanup cmp2lcu.v 2020-04-03 14:28:22 -07:00
Eddie Hung 9b63700678 techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
Eddie Hung fffe42d4c1 cmp2lut: comment out unused since 362f4f9 2020-04-03 14:28:04 -07:00
whitequark 763401fc82 ecp5: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
whitequark ebee746ad2 ice40: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
Eddie Hung 5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings 
IdString: use more ID::*, make them easier to use, speed up IdString::in()
 2020-04-02 11:47:25 -07:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Marcin Kościelnicki 0ed1062557 simcells.v: Generate the fine FF cell types by a python script. 
This makes adding more FF types in the future much more manageable.

Fixes #1824.
 2020-04-02 18:37:15 +02:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Alberto Gonzalez fc6b898178
Fix indentation in `techlibs/ice40/synth_ice40.cc`. 2020-04-01 16:29:56 +00:00
David Shah beab15b77c
Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix 
ice40: Map unmapped 'mince' DFFs to gate level
 2020-03-21 17:35:27 +00:00
Sylvain Munaut c15ce5a73e ice40: Fix typos in SPRAM ABC9 timing specs 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-20 22:19:55 +01:00
David Shah e813624f21 ice40: Map unmapped 'mince' DFFs to gate level 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-20 20:29:16 +00:00
Marcin Kościelnicki 9b982e929c xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
Sylvain Munaut acd9eeef7c ice40: Fix SPRAM model to keep data stable if chipselect is low 
According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-14 21:01:42 +01:00
Miodrag Milanovic acb341745d Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
N. Engelhardt 282d331e7e
Merge pull request #1716 from zeldin/ecp5_fix 
ecp5: remove unused parameter from \$__ECP5_PDPW16KD
 2020-03-09 11:04:08 +01:00
N. Engelhardt 8a39a580e1 remove unused parameters 2020-03-06 16:45:36 +01:00
Eddie Hung 69f1555058 ice40: fix specify for ICE40_{LP,U} 2020-03-05 08:11:49 -08:00
Eddie Hung 0930c00f03 ice40: fix implicit signal in specify, also clamp negative times to 0 2020-03-04 15:28:17 -08:00
Eddie Hung 6eb528277e
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1 
xilinx: cleanup DSP48E1 handling for abc9
 2020-03-04 13:37:09 -08:00
Eddie Hung 7b543fdb0c xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
Eddie Hung 512596760b xilinx: cleanup DSP48E1 handling for abc9 2020-03-04 11:31:12 -08:00
Eddie Hung f65fc845e5 xilinx: improve specify for DSP48E1 2020-03-04 11:31:12 -08:00
Eddie Hung 78d4fff69d xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v 2020-03-04 11:31:12 -08:00
N. Engelhardt 0ec971444b
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc 
Add -flowmap option to `synth{,_ice40}`
 2020-03-03 19:15:41 +01:00
Eddie Hung 4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
R. Ou 7932672fc2 coolrunner2: Attempt to give wires/cells more meaningful names 2020-03-02 01:40:57 -08:00
R. Ou b9c98e0100 coolrunner2: Fix invalid multiple fanouts of XOR/OR gates 
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:

module top(input a, input b, input clk_, output reg o, output o2);

wire clk;

BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

always @(posedge clk)
    o = a ^ b;
assign o2 = a ^ b;

endmodule
 2020-03-02 01:07:15 -08:00
R. Ou a618004897 coolrunner2: Fix packed register+input buffer insertion 
The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.
 2020-03-02 00:32:57 -08:00
R. Ou a6aeee4e1a coolrunner2: Insert many more required feedthrough cells 2020-03-01 16:56:21 -08:00
Dan Ravensloft d7987fec12 Add -flowmap to synth and synth_ice40 2020-02-28 14:29:57 +00:00
Eddie Hung 090e54569a Remove RAMB{18,36}E1 from cells_xtra.py 2020-02-27 10:33:04 -08:00
Eddie Hung 376319dc8d xilinx: Update RAMB* specify entries 2020-02-27 10:17:29 -08:00
Eddie Hung 6bd9550100 ice40: add delays to SB_CARRY 2020-02-27 10:17:29 -08:00
Eddie Hung 3b74e0fa45 xilinx: add delays to INV 2020-02-27 10:17:29 -08:00
Eddie Hung aa969f8778 More +/ice40/cells_sim.v fixes 2020-02-27 10:17:29 -08:00
Eddie Hung b0ffd9cd8b Make +/xilinx/cells_sim.v legal 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung 3ea5506f81 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung 7d86aceee3 Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy 2020-02-27 10:17:29 -08:00
Eddie Hung 3728ef1765 ice40: fix specify for inverted clocks 2020-02-27 10:17:29 -08:00
Eddie Hung aac309626b Fix tests by gating some specify constructs from iverilog 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung a76520112d ice40: specify fixes 2020-02-27 10:17:29 -08:00
Eddie Hung fb60d82971 ice40: move over to specify blocks for -abc9 2020-02-27 10:17:29 -08:00
Eddie Hung a85c55113f synth_ecp5: use +/abc9_model.v 2020-02-27 10:17:29 -08:00
Eddie Hung 8408c13405 Update xilinx for ABC9 2020-02-27 10:17:29 -08:00
Eddie Hung ac24a23e31 Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
Eddie Hung d2284715fa ecp5: remove small LUT entries 2020-02-27 10:17:29 -08:00
Eddie Hung ccc84f8923 Fix commented out specify statement 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 46a89d7264 ecp5: deprecate abc9_{arrival,required} and *.{lut,box} 2020-02-27 10:17:29 -08:00
Eddie Hung 577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00
Eddie Hung 0e7c55e2a7 Auto-generate .box/.lut files from specify blocks 2020-02-27 10:17:29 -08:00
Eddie Hung 74f49b1f55 abc9_ops: -prep_box, to be called once 2020-02-27 10:17:29 -08:00
Eddie Hung 5643c1b8c5 abc9_ops: -prep_lut and -write_lut to auto-generate LUT library 2020-02-27 10:17:29 -08:00
Claire Wolf ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter 
Improve CoolRunner-II optimization by using extract_counter pass
 2020-02-27 19:05:56 +01:00
Claire Wolf 47228feb77
Merge pull request #1708 from rqou/coolrunner2-buf-fix 
coolrunner2: Separate and improve buffer cell insertion pass
 2020-02-27 19:03:59 +01:00
Piotr Binkowski 62ab100c61 xilinx: mark IOBUFDSE3 IOB pin as external 2020-02-27 13:15:57 +01:00
Marcus Comstedt 48a9b4f616 ecp5: Add missing parameter to \$__ECP5_PDPW16KD 2020-02-22 15:51:25 +01:00
R. Ou 13d0ff4a5f coolrunner2: Use extract_counter to optimize counters 
This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
 2020-02-17 03:09:40 -08:00
R. Ou 6a0682f5a0 coolrunner2: Separate and improve buffer cell insertion pass 
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
 2020-02-16 20:25:46 -08:00
Miodrag Milanovic cd5c177739 Remove executable flag from files 2020-02-15 10:36:44 +01:00
Eddie Hung 00d41905df abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr 2020-02-13 12:33:58 -08:00
Eddie Hung c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00
Eddie Hung 2e8d6ec0b0 Remove unnecessary comma 2020-02-07 12:45:07 -08:00
Eddie Hung affae35847 techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00
Marcin Kościelnicki 89adef352f xilinx: Add support for LUT RAM on LUT4-based devices. 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki d48950d92d xilinx: Initial support for LUT4 devices. 
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
 2020-02-07 09:03:22 +01:00
Eddie Hung 1f54b0008f
Merge pull request #1685 from dh73/gowin 
Removing cells_sim from GoWin bram techmap
 2020-02-06 20:59:21 -08:00
Marcin Kościelnicki 30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki 95c46ccc55 xilinx: Add support for Spartan 3A DSP block RAMs. 
Part of #1550
 2020-02-07 01:00:29 +01:00
Eddie Hung 1784d25f53
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map 
Fix/cleanup +/xilinx/arith_map.v
 2020-02-06 13:51:23 -08:00
Diego H 87883f6d88 Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
Eddie Hung d625e399cb Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk 2020-02-06 11:25:07 -08:00
Eddie Hung 5ecbc6c7b2 Fix/cleanup +/xilinx/arith_map.v 2020-02-06 11:00:04 -08:00
whitequark 081d9318bc ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 16:52:51 +00:00
whitequark 3f4460a186 ice40: match memory inference attribute values case insensitive. 
LSE/Synplify use case insensitive matching.
 2020-02-06 14:58:20 +00:00
whitequark fc28bf55aa ice40: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify appear to interpret attribute values insensitive
    to case. There is currently no way to do this in Yosys (attrmap
    can only change case of attribute names).
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 14:58:20 +00:00
Eddie Hung 0b0148399c synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
Eddie Hung 4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung 0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Marcin Kościelnicki b44d0e041f xilinx: use RAM32M/RAM64M for memories with two read ports 
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
 2020-02-02 14:34:21 +01:00
Claire Wolf 5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental 
Add log_experimental() and experimental() API and "yosys -x"
 2020-01-29 15:25:03 +01:00
Eddie Hung c5971cb16c synth_xilinx: cleanup help 2020-01-28 17:48:43 -08:00
Eddie Hung 0fd64aab25 synth_xilinx: fix help when no active_design; fixes #1664 2020-01-28 17:41:57 -08:00
Marcin Kościelnicki 7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Eddie Hung 7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Eddie Hung 245b8c4ab6 Fix unresolved conflict from #1573 2020-01-28 10:17:47 -08:00
N. Engelhardt 086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
Eddie Hung e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Eddie Hung af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings 
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
 2020-01-27 09:54:04 -08:00
Claire Wolf cef607c8b7 Add log_experimental() and experimental() API and "yosys -x" 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-27 18:27:47 +01:00
Eddie Hung 81e6b040a4 ice40: add SB_SPRAM256KA arrival time 2020-01-24 12:17:09 -08:00
Eddie Hung b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung 7858cf20a9 Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-23 19:02:27 -08:00
Eddie Hung da134701cd Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-22 14:22:03 -08:00
Eddie Hung 72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung 152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung 8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung 7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map 
Cleanup +/xilinx/arith_map.v
 2020-01-18 09:11:52 -08:00
David Shah a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning 
ice40: Demote conflicting FF init values to a warning
 2020-01-18 09:47:17 +00:00
Eddie Hung 78ffd5d193 synth_ice40: call wreduce before mul2dsp 2020-01-17 15:41:55 -08:00
Eddie Hung 5c589244df Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
Eddie Hung 1e6d56dca1 +/xilinx/arith_map.v fix $lcu rule 2020-01-17 11:28:37 -08:00
Eddie Hung b0605128b6 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-15 16:42:27 -08:00
Eddie Hung 03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung 5a63c19747 abc9_ops: -write_box is empty, output a dummy box to prevent ABC error 2020-01-15 13:14:48 -08:00
Miodrag Milanović abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W 
synth_xilinx: fix default W value for non-xc7
 2020-01-15 08:47:16 +01:00
Eddie Hung 0e4285ca0d abc9_ops: generate flop box ids, add abc9_required to FD* cells 2020-01-14 15:05:49 -08:00
Eddie Hung 915e7dde73 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-14 12:57:56 -08:00
Eddie Hung d21262ee04 Adding (* techmap_autopurge *) to FD* in abc9_map.v 2020-01-14 12:22:21 -08:00
Eddie Hung 36d1a2c60f synth_xilinx: fix default W value for non-xc7 2020-01-14 11:34:40 -08:00
Miodrag Milanović 9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung f9aae90e7a Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-12 15:19:41 -08:00
Eddie Hung c0b55deb0b synth_ice40: -abc2 to always use `abc` even if `-abc9` 2020-01-12 11:26:05 -08:00
Eddie Hung 35e49fde4d Another conflict 2020-01-11 18:57:25 -08:00
Eddie Hung c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Eddie Hung 28f814ee59 Add abc9_required to DSP48E1.{A,B,C,D,PCIN} 2020-01-10 17:12:31 -08:00
Eddie Hung 7d94e18100 synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro 2020-01-10 15:07:46 -08:00
Eddie Hung 475d983676 abc9_ops -prep_times: generate flop boxes from abc9_required attr 2020-01-10 14:49:52 -08:00
Eddie Hung b2259a9201 Add abc9_ops -check, -prep_times, -write_box for required times 2020-01-10 11:45:41 -08:00
Miodrag Milanovic 992b507537 Use CARRY4 for abc1 as well, preventing issues with Vivado 2020-01-10 12:34:21 +01:00
Eddie Hung 57f6826e29 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-08 18:30:20 -08:00
Eddie Hung 823a08e0d8 Fix abc9_xc7.box comments 2020-01-07 17:00:38 -08:00
Eddie Hung 6e3e814025 Fix abc9_xc7.box comments 2020-01-07 15:59:18 -08:00
Eddie Hung 94ab3791ce Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs 2020-01-07 15:44:18 -08:00
Eddie Hung 5c89dead5f Merge branch 'master' of github.com:YosysHQ/yosys 2020-01-06 16:51:32 -08:00
Eddie Hung 01866a7909 Fix DSP48E1 sim 2020-01-06 16:45:29 -08:00
Eddie Hung 53aa51dc92 Re-enable &mfs for synth_{ecp5,xilinx} 2020-01-06 16:21:04 -08:00
Eddie Hung 98ee8c14df Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
Eddie Hung 66698cb6fd
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor 
Refactor abc9's DSP48E1 handling
 2020-01-06 15:00:16 -08:00
Eddie Hung 28bf712372 Wrap arrival functions inside `YOSYS too 2020-01-06 11:55:56 -08:00
Eddie Hung 27c150bfcc Fix return value of arrival time functions, fix word 2020-01-06 11:39:08 -08:00
Eddie Hung 020606f81c Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required 2020-01-06 09:44:00 -08:00
Eddie Hung 19541640ee Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 09:31:28 -08:00
Miodrag Milanovic c5d28f5d6b Valid to have attribute starting with SB_CARRY. 2020-01-04 19:00:44 +01:00
Eddie Hung bac1e65a9c Fix spacing 2020-01-02 17:21:54 -08:00
Eddie Hung c28bea0382 Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor 2020-01-02 15:57:35 -08:00
Eddie Hung 5f97086302 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-02 15:14:12 -08:00
Eddie Hung 50b68777d3 Drive $[ABCD] explicitly 2020-01-02 13:28:37 -08:00
whitequark f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming 
Harmonize BRAM/LUTRAM descriptions across all of Yosys
 2020-01-02 21:06:17 +00:00
Eddie Hung a051801b72 synth_xilinx -dff to work with abc too 2020-01-02 12:53:26 -08:00
Eddie Hung 3012e9eebc Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor 2020-01-02 12:48:07 -08:00
Eddie Hung b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung ec1756c094 Update comments 2020-01-02 12:39:52 -08:00
Eddie Hung 8e507bd807 abc9 -keepff -> -dff; refactor dff operations 2020-01-02 12:36:54 -08:00
Eddie Hung d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime 
"abc -dff" to no longer retime by default
 2020-01-02 08:46:24 -08:00
Eddie Hung d0d3ab8f67 ifndef __ICARUS__ -> ifdef YOSYS 2020-01-01 17:33:47 -08:00
Eddie Hung 3d98a96273 ifdef __ICARUS__ -> ifndef YOSYS 2020-01-01 17:33:10 -08:00
Eddie Hung db04161eca Rework abc9's DSP48E1 model 2020-01-01 17:30:26 -08:00
Eddie Hung 3deec51ddc Fix anlogic async flop mapping 2020-01-01 08:43:16 -08:00
Eddie Hung 0e95756e96 Clamp -46ps for FDPE* too 2020-01-01 08:39:00 -08:00
Eddie Hung c40b1aae42 Restore abc9 -keepff 2020-01-01 08:34:43 -08:00
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys. 
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
 2020-01-01 12:30:00 +00:00
Eddie Hung 44d9fb0e7c Re-arrange FD order 2019-12-31 18:47:38 -08:00
Eddie Hung f7793a2956 Missing character 2019-12-31 18:42:11 -08:00
Eddie Hung 35c659be74 Cleanup xilinx boxes 2019-12-31 18:29:44 -08:00
Eddie Hung 2358320f51 Cleanup ice40 boxes 2019-12-31 18:29:37 -08:00
Eddie Hung b2046a2114 Cleanup ecp5 boxes 2019-12-31 18:29:29 -08:00
Eddie Hung 6b825c719b Update abc9_xc7.box comments 2019-12-31 15:25:46 -08:00
Eddie Hung 4cdba00e25 FDCE ports to be alphabetical 2019-12-31 15:24:02 -08:00
Eddie Hung b4663a987b Fix attributes on $__ABC9_ASYNC[01] whitebox 2019-12-31 11:14:11 -08:00
Eddie Hung 789211d9b3 Fix incorrect $__ABC9_ASYNC[01] box 2019-12-31 11:13:50 -08:00
Niklas Nisbeth 379dcda139 ice40: Demote conflicting FF init values to a warning 2019-12-31 02:38:10 +01:00
Eddie Hung 7649ec72c9 Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor 2019-12-30 16:20:58 -08:00
Eddie Hung 543bd2de6c Update timings for Xilinx S7 cells 2019-12-30 14:36:07 -08:00
Eddie Hung eb4e767053 Do not offset FD* box timings due to -46ps Tsu 2019-12-30 14:35:10 -08:00
Eddie Hung 405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Eddie Hung a038294a87 Tidy up abc9_map.v 2019-12-30 14:19:29 -08:00
Eddie Hung d7ada66497 Add "synth_xilinx -dff" option, cleanup abc9 2019-12-30 14:13:16 -08:00
Eddie Hung 79448f9be0 Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
Eddie Hung c9e3b26412 Disable synth_gowin -abc9 as it offers no advantages yet 2019-12-30 13:28:29 -08:00
Eddie Hung aa6d06c1b5 Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" 
This reverts commit 6008bb7002.
 2019-12-30 13:28:29 -08:00
Miodrag Milanović c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Miodrag Milanovic 8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Eddie Hung 71906fab51 Nitpick cleanup for ecp5 2019-12-27 16:57:08 -08:00
Eddie Hung b7afafde22 Consistency 2019-12-27 14:52:26 -08:00
Eddie Hung 4eaa45091c Update some abc9_arrival times, add abc9_required times 2019-12-27 14:47:50 -08:00
Marcin Kościelnicki 13a3041030
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen 
xilinx_dsp: Initial DSP48A/DSP48A1 support.
 2019-12-25 16:18:44 +01:00
Marcin Kościelnicki dadaf7ed78 xilinx: Test our DSP48A/DSP48A1 simulation models. 2019-12-23 20:36:43 +01:00
Marcin Kościelnicki 666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Miodrag Milanovic 436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic 1937091f62 iopad no op for compatibility with old scripts 2019-12-21 13:21:45 +01:00
Miodrag Milanovic 2fcf683af4 Make iopad option default for all xilinx flows 2019-12-21 11:56:41 +01:00
Eddie Hung d3fc94405f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 14:07:23 -08:00
Eddie Hung 5986a4df40 Add abc9_arrival times for RAM{32,64}M 2019-12-20 14:06:59 -08:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 7928eb113c Add RAM{32,64}M to abc9_map.v 2019-12-20 13:41:23 -08:00
Eddie Hung 10e82e103f
Revert "Optimise write_xaiger" 2019-12-20 12:05:45 -08:00
Eddie Hung 45f0f1486b Add RAM{32,64}M to abc9_map.v 2019-12-19 11:24:39 -08:00
Eddie Hung 979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup 
Optimise write_xaiger
 2019-12-19 12:24:03 -05:00
Marcin Kościelnicki 8b2c9f4518 xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
Marcin Kościelnicki 561ae1c5c4 xilinx_dffopt: Keep order of LUT inputs. 
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
 2019-12-19 18:01:43 +01:00
David Shah 520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld 
ecp5: Add support for mapping PRLD FFs
 2019-12-18 19:42:17 +00:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung 5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung d910bec8e0 Update xc7/xcu bram rules 2019-12-16 13:00:58 -08:00
Eddie Hung 5d00996426 Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00
Eddie Hung 7545ab3814 Populate DID/DOD even if unused 2019-12-16 11:57:04 -08:00
Eddie Hung c4d37813cb Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q 2019-12-16 10:41:13 -08:00
Diego H f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Eddie Hung 52875b0d61
Merge pull request #1533 from dh73/bram_xilinx 
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
 2019-12-13 12:01:03 -08:00
Eddie Hung c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches 2019-12-13 08:59:17 -08:00
Eddie Hung d6514fc2e1 RAM64M8 to also have [5:0] for address 2019-12-13 08:54:19 -08:00
Eddie Hung dd7d2d8db6 Duplicate tribuf call, credit to @mwkmwkmwk 2019-12-13 08:51:05 -08:00
Eddie Hung 8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung 50e0c83560 Fix RAM64M model to have 6 bit address bus 2019-12-12 18:52:03 -08:00
Eddie Hung 7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Diego H 751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung 9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung 3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Eddie Hung 3bd623bb05 synth_xilinx: error out if tristate without '-iopad' 2019-12-12 14:33:33 -08:00
Diego H 937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H ab6ac8327f Merge https://github.com/YosysHQ/yosys into bram_xilinx 2019-12-12 13:40:05 -06:00
Eddie Hung f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
David Shah 613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping 
Intel housekeeping
 2019-12-11 08:46:10 +00:00
Dan Ravensloft 85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
Dan Ravensloft eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Eddie Hung 7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung 49c2e59b2a Fix comment 2019-12-09 15:44:19 -08:00
Eddie Hung fb203d2a2c ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
Eddie Hung 500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
David Shah 184c0e796a ecp5: Add support for mapping PRLD FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 13:04:36 +00:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung 98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung 02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Eddie Hung 864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Eddie Hung 0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung 19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung 258a34e6f1 Oh deary me 2019-12-04 20:33:24 -08:00
Eddie Hung b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung 31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
Marcin Kościelnicki fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Marcin Kościelnicki 10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Eddie Hung a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung f98aa1c13f Revert "Add INIT value to abc9_control" 
This reverts commit 19bfb41958.
 2019-12-03 15:40:44 -08:00
Eddie Hung ed3f359175 $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve 
name and attr
 2019-12-03 14:49:10 -08:00
Eddie Hung 1ea9ce0ad7 ice40_opt to ignore (* keep *) -ed cells 2019-12-03 14:48:39 -08:00
Eddie Hung 0add5965c7 techmap abc_unmap.v before xilinx_srl -fixed 2019-12-03 14:27:45 -08:00
Clifford Wolf 2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
Eddie Hung 19bfb41958 Add INIT value to abc9_control 2019-12-02 14:17:06 -08:00
Marcin Kościelnicki 2badaa9adb xilinx: Add missing blackbox cell for BUFPLL. 2019-11-29 16:56:27 +01:00
Eddie Hung b1ab7c16c4 clkpart -unpart into 'finalize' 2019-11-28 12:59:43 -08:00
Diego H 3a5a65829c Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-27 12:05:04 -06:00
Eddie Hung df8dc6d1fb ean call after abc{,9} 2019-11-27 09:10:34 -08:00
Eddie Hung f6c0ec1d09 Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff 2019-11-27 01:03:33 -08:00
Eddie Hung 739f530906 Move 'clean' from map_luts to finalize 2019-11-26 14:51:39 -08:00
Marcin Kościelnicki 0466c48533 xilinx: Add simulation models for IOBUF and OBUFT. 2019-11-26 08:15:20 +01:00
Eddie Hung d087024caf Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-25 12:42:09 -08:00
Eddie Hung 6a2eb5d8f9 Special abc9_clock wire to contain only clock signal 2019-11-25 12:36:13 -08:00
Marcin Kościelnicki 6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki 7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos 72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos 6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Eddie Hung eb11c06a69 For abc9, run clkpart before ff_map and after abc9 2019-11-23 10:18:22 -08:00
Martin Pietryka 97b22413e5 coolrunner2: remove spurious log_pop() call, fixes #1463 
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
 2019-11-23 06:21:40 +01:00
Eddie Hung bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Marcin Kościelnicki 1d098b7195 gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Eddie Hung 5a30e3ac3b Merge branch 'eddie/xaig_dff_adff' into xaig_dff 2019-11-21 16:15:25 -08:00
Eddie Hung af3055fe83 Add blackbox model for $__ABC9_FF_ so that clock partitioning works 2019-11-20 14:30:56 -08:00
Eddie Hung df63d75ff3 Fix INIT values 2019-11-20 11:26:59 -08:00
Eddie Hung 344619079d Do not drop async control signals in abc_map.v 2019-11-19 16:57:07 -08:00
Eddie Hung 09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Clifford Wolf 7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Pepijn de Vos 8ab412eb16 Remove dff init altogether 
The hardware does not actually support it.
In reality it is always initialised to its reset value.
 2019-11-19 15:53:44 +01:00
Marcin Kościelnicki 7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. 
This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
 2019-11-19 01:00:58 +01:00
Pepijn de Vos dd8c7e1ddd add help for nowidelut and abc9 options 2019-11-18 14:26:09 +01:00
Pepijn de Vos 32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
David Shah 51e4e29bb1 ecp5: Use new autoname pass for better cell/net names 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-15 21:03:11 +00:00
Clifford Wolf e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf 056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim 
ice40: Support for post-place-and-route timing simulations
 2019-11-14 12:07:25 +01:00