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ecp5: (* abc9_flop *) gated behind YOSYS

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Eddie Hung 2020-04-14 10:36:07 -07:00
parent 509de98468
commit a52f779eca
1 changed files with 2 additions and 0 deletions
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2
techlibs/ecp5/cells_sim.v
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@ -294,7 +294,9 @@ endmodule
// ---------------------------------------
`ifdef YOSYS
(* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *)
`endif
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";