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Fix invalid verilog syntax

This commit is contained in:
Miodrag Milanovic 2020-03-14 14:33:44 +01:00
parent 569e834df2
commit acb341745d
1 changed files with 1 additions and 1 deletions
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2
techlibs/common/gate2lut.v
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@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y);
// A 1010 1010
// B 1100 1100
// S 1111 0000
.LUT(8'b_1100_1010)
.LUT(8'b 1100_1010)
) lut (
.A(AA),
.Y(Y)