mirror of https://github.com/YosysHQ/yosys.git
xilinx: improve specify for DSP48E1
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@ -3063,7 +3063,6 @@ module DSP48E1 (
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`ifdef YOSYS
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function integer \A.required ;
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begin
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\A.required = 0;
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if (AREG != 0) \A.required = 254;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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if (MREG != 0) \A.required = 1416;
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@ -3083,7 +3082,6 @@ module DSP48E1 (
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endfunction
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function integer \B.required ;
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begin
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\B.required = 0;
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if (BREG != 0) \B.required = 324;
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else if (MREG != 0) \B.required = 1285;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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@ -3099,14 +3097,12 @@ module DSP48E1 (
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endfunction
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function integer \C.required ;
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begin
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\C.required = 0;
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if (CREG != 0) \C.required = 168;
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else if (PREG != 0) \C.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ;
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end
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endfunction
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function integer \D.required ;
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begin
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\D.required = 0;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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end
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
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@ -3119,15 +3115,8 @@ module DSP48E1 (
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end
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end
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endfunction
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function integer \PCIN.required ;
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begin
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\PCIN.required = 0;
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if (PREG != 0) \PCIN.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025) ;
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end
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endfunction
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function integer \P.arrival ;
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begin
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\P.arrival = 0;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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if (PREG != 0) \P.arrival = 329;
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// Worst-case from CREG and MREG
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@ -3155,13 +3144,10 @@ module DSP48E1 (
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else if (AREG != 0) \P.arrival = 1632;
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else if (BREG != 0) \P.arrival = 1616;
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end
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//else
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// $error("Invalid DSP48E1 configuration");
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end
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endfunction
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function integer \PCOUT.arrival ;
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begin
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\PCOUT.arrival = 0;
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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if (PREG != 0) \PCOUT.arrival = 435;
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// Worst-case from CREG and MREG
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@ -3189,27 +3175,125 @@ module DSP48E1 (
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else if (AREG != 0) \PCOUT.arrival = 1780;
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else if (BREG != 0) \PCOUT.arrival = 1765;
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end
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//else
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// $error("Invalid DSP48E1 configuration");
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end
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endfunction
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function integer \A.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
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end
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endfunction
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function integer \A.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
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end
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endfunction
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function integer \B.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
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end
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endfunction
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function integer \B.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
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end
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endfunction
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function integer \C.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
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end
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endfunction
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function integer \C.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
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else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
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end
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endfunction
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function integer \D.P.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
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end
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endfunction
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function integer \D.PCOUT.comb ;
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begin
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
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end
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endfunction
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specify
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$setup(A , posedge CLK &&& !IS_CLK_INVERTED, \A.required () );
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$setup(A , negedge CLK &&& IS_CLK_INVERTED, \A.required () );
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$setup(B , posedge CLK &&& !IS_CLK_INVERTED, \B.required () );
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$setup(B , negedge CLK &&& IS_CLK_INVERTED, \B.required () );
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$setup(C , posedge CLK &&& !IS_CLK_INVERTED, \C.required () );
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$setup(C , negedge CLK &&& IS_CLK_INVERTED, \C.required () );
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$setup(D , posedge CLK &&& !IS_CLK_INVERTED, \D.required () );
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$setup(D , negedge CLK &&& IS_CLK_INVERTED, \D.required () );
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$setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, \PCIN.required () );
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$setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, \PCIN.required () );
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if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ;
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if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ;
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if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
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if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
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endspecify
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generate
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if (PREG == 0 && MREG == 0 && AREG == 0)
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specify
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(A *> P) = \A.P.comb ();
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(A *> PCOUT) = \A.PCOUT.comb ();
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endspecify
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else
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specify
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$setup(A, posedge CLK &&& !IS_CLK_INVERTED, \A.required () );
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$setup(A, negedge CLK &&& IS_CLK_INVERTED, \A.required () );
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endspecify
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if (PREG == 0 && MREG == 0 && BREG == 0)
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specify
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(B *> P) = \B.P.comb ();
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(B *> PCOUT) = \B.PCOUT.comb ();
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endspecify
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else
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specify
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$setup(B, posedge CLK &&& !IS_CLK_INVERTED, \B.required () );
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$setup(B, negedge CLK &&& IS_CLK_INVERTED, \B.required () );
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endspecify
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if (PREG == 0 && CREG == 0)
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specify
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(C *> P) = \C.P.comb ();
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(C *> PCOUT) = \C.PCOUT.comb ();
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endspecify
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else
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specify
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$setup(C, posedge CLK &&& !IS_CLK_INVERTED, \C.required () );
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$setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () );
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endspecify
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if (PREG == 0 && MREG == 0 && DREG == 0)
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specify
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(D *> P) = \D.P.comb ();
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(D *> PCOUT) = \D.PCOUT.comb ();
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endspecify
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else
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specify
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$setup(D, posedge CLK &&& !IS_CLK_INVERTED, \D.required () );
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$setup(D, negedge CLK &&& IS_CLK_INVERTED, \D.required () );
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endspecify
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if (PREG == 0)
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specify
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(PCIN *> P) = 1107;
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(PCIN *> PCOUT) = 1255;
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endspecify
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else
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specify
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$setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025);
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$setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025);
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endspecify
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if (PREG || AREG || BREG || CREG || DREG || MREG)
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specify
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if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ;
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if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ;
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if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
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if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
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endspecify
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endgenerate
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`endif
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initial begin
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