mirror of https://github.com/YosysHQ/yosys.git
simcells.v: Generate the fine FF cell types by a python script.
This makes adding more FF types in the future much more manageable. Fixes #1824.
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TEMPLATES = [
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SR_{S:N|P}{R:N|P}_ (S, R, Q)
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//-
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//- A set-reset latch with {S:negative|positive} polarity SET and {R:negative|positive} polarity RESET.
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//-
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//- Truth table: S R | Q
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//- -----+---
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//- {S:0|1} {R:0|1} | x
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//- {S:0|1} {R:1|0} | 1
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//- {S:1|0} {R:0|1} | 0
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//- {S:1|0} {R:1|0} | y
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//-
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module \$_SR_{S:N|P}{R:N|P}_ (S, R, Q);
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input S, R;
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output reg Q;
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always @({S:neg|pos}edge S, {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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end
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endmodule
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""",
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"""
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`ifdef SIMCELLS_FF
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_FF_ (D, Q)
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//-
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//- A D-type flip-flop that is clocked from the implicit global clock. (This cell
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//- type is usually only used in netlists for formal verification.)
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//-
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module \$_FF_ (D, Q);
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input D;
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output reg Q;
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always @($global_clock) begin
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Q <= D;
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end
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endmodule
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`endif
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFF_{C:N|P}_ (D, C, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop.
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//-
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//- Truth table: D C | Q
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//- -----+---
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//- d {C:\\|/} | d
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//- - - | q
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//-
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module \$_DFF_{C:N|P}_ (D, C, Q);
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input D, C;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {E:negative|positive} polarity enable.
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//-
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//- Truth table: D C E | Q
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//- -------+---
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//- d {C:\\|/} {E:0|1} | d
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//- - - - | q
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//-
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module \$_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q);
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input D, C, E;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if ({E:!E|E}) Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set}.
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//-
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//- Truth table: D C R | Q
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//- -------+---
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//- - - {R:0|1} | {V:0|1}
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//- d {C:\\|/} - | d
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//- - - - | q
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//-
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module \$_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
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input D, C, R;
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output reg Q;
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always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
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//- polarity reset.
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//-
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//- Truth table: C S R D | Q
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//- ---------+---
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//- - - {R:0|1} - | 0
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//- - {S:0|1} - - | 1
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//- {C:\\|/} - - d | d
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//- - - - - | q
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//-
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module \$_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q);
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input C, S, R, D;
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output reg Q;
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always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCH_{E:N|P}_ (E, D, Q)
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//-
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//- A {E:negative|positive} enable D-type latch.
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//-
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//- Truth table: E D | Q
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//- -----+---
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//- {E:0|1} d | d
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//- - - | q
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//-
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module \$_DLATCH_{E:N|P}_ (E, D, Q);
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input E, D;
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output reg Q;
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always @* begin
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if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
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//-
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//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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//- - - {R:0|1} - | 0
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//- - {S:0|1} - - | 1
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//- {E:0|1} - - d | d
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//- - - - - | q
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//-
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module \$_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q);
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input E, S, R, D;
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output reg Q;
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always @* begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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]
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lines = []
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with open('simcells.v') as f:
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for l in f:
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lines.append(l)
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if 'START AUTOGENERATED CELL TYPES' in l:
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break
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with open('simcells.v', 'w') as f:
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for l in lines:
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f.write(l)
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for template in TEMPLATES:
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chunks = []
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vars = {}
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pos = 0
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while pos < len(template):
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if template[pos] != '{':
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np = template.find('{', pos)
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if np == -1:
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np = len(template)
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chunks.append(template[pos:np])
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pos = np
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else:
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np = template.index('}', pos)
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sub = template[pos + 1:np]
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pos = np + 1
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var, _, vals = sub.partition(':')
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if not vals:
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raise ValueError(sub)
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vals = vals.split('|')
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if var not in vars:
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vars[var] = len(vals)
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else:
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if vars[var] != len(vals):
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raise ValueError(vars[var], vals)
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chunks.append((var, vals))
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combs = [{}]
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for var in vars:
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combs = [
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{
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var: i,
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**comb,
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}
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for comb in combs
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for i in range(vars[var])
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]
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for comb in combs:
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f.write(
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''.join(
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c if isinstance(c, str) else c[1][comb[c[0]]]
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for c in chunks
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)
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)
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@ -456,11 +456,16 @@ output Y;
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assign Y = E ? A : 1'bz;
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endmodule
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// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually,
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// instead edit the templates in gen_ff_types.py and rerun it.
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// START AUTOGENERATED CELL TYPES
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SR_NN_ (S, R, Q)
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//-
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//- A set-reset latch with negative polarity SET and RESET.
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//- A set-reset latch with negative polarity SET and negative polarity RESET.
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//-
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//- Truth table: S R | Q
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//- -----+---
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@ -532,7 +537,7 @@ endmodule
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//-
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//- $_SR_PP_ (S, R, Q)
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//-
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//- A set-reset latch with positive polarity SET and RESET.
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//- A set-reset latch with positive polarity SET and positive polarity RESET.
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//-
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//- Truth table: S R | Q
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//- -----+---
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@ -871,7 +876,8 @@ endmodule
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//-
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//- $_DFFSR_NNN_ (C, S, R, D, Q)
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//-
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//- A negative edge D-type flip-flop with negative polarity set and reset.
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//- A negative edge D-type flip-flop with negative polarity set and negative
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//- polarity reset.
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//-
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//- Truth table: C S R D | Q
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//- ---------+---
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@ -951,7 +957,8 @@ endmodule
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//-
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//- $_DFFSR_NPP_ (C, S, R, D, Q)
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//-
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//- A negative edge D-type flip-flop with positive polarity set and reset.
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//- A negative edge D-type flip-flop with positive polarity set and positive
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//- polarity reset.
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//-
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//- Truth table: C S R D | Q
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//- ---------+---
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@ -977,7 +984,8 @@ endmodule
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//-
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//- $_DFFSR_PNN_ (C, S, R, D, Q)
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//-
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//- A positive edge D-type flip-flop with negative polarity set and reset.
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//- A positive edge D-type flip-flop with negative polarity set and negative
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//- polarity reset.
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//-
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//- Truth table: C S R D | Q
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//- ---------+---
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@ -1057,7 +1065,8 @@ endmodule
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//-
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//- $_DFFSR_PPP_ (C, S, R, D, Q)
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//-
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//- A positive edge D-type flip-flop with positive polarity set and reset.
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//- A positive edge D-type flip-flop with positive polarity set and positive
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//- polarity reset.
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//-
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//- Truth table: C S R D | Q
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//- ---------+---
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@ -1123,7 +1132,8 @@ endmodule
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//-
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//- $_DLATCHSR_NNN_ (E, S, R, D, Q)
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//-
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//- A negative enable D-type latch with negative polarity set and reset.
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//- A negative enable D-type latch with negative polarity set and negative
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1149,8 +1159,8 @@ endmodule
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//-
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//- $_DLATCHSR_NNP_ (E, S, R, D, Q)
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//-
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//- A negative enable D-type latch with negative polarity set and positive polarity
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//- reset.
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//- A negative enable D-type latch with negative polarity set and positive
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1176,8 +1186,8 @@ endmodule
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//-
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//- $_DLATCHSR_NPN_ (E, S, R, D, Q)
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//-
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//- A negative enable D-type latch with positive polarity set and negative polarity
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//- reset.
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//- A negative enable D-type latch with positive polarity set and negative
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1203,7 +1213,8 @@ endmodule
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//-
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//- $_DLATCHSR_NPP_ (E, S, R, D, Q)
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//-
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//- A negative enable D-type latch with positive polarity set and reset.
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//- A negative enable D-type latch with positive polarity set and positive
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1229,7 +1240,8 @@ endmodule
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//-
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//- $_DLATCHSR_PNN_ (E, S, R, D, Q)
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//-
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//- A positive enable D-type latch with negative polarity set and reset.
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//- A positive enable D-type latch with negative polarity set and negative
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1255,8 +1267,8 @@ endmodule
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//-
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//- $_DLATCHSR_PNP_ (E, S, R, D, Q)
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//-
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//- A positive enable D-type latch with negative polarity set and positive polarity
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//- reset.
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//- A positive enable D-type latch with negative polarity set and positive
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1282,8 +1294,8 @@ endmodule
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//-
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//- $_DLATCHSR_PPN_ (E, S, R, D, Q)
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//-
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//- A positive enable D-type latch with positive polarity set and negative polarity
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//- reset.
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//- A positive enable D-type latch with positive polarity set and negative
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1309,7 +1321,8 @@ endmodule
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//-
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//- $_DLATCHSR_PPP_ (E, S, R, D, Q)
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//-
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//- A positive enable D-type latch with positive polarity set and reset.
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//- A positive enable D-type latch with positive polarity set and positive
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//- polarity reset.
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//-
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//- Truth table: E S R D | Q
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//- ---------+---
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@ -1330,4 +1343,3 @@ always @* begin
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Q <= D;
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end
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endmodule
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