mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
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clairexen
GitHub
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d9dd8bc748
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@ -143,78 +143,46 @@ module _90_shift_shiftx (A, B, Y);
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localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
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wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
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generate
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`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
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// If $shift/$shiftx only shifts in units of Y_WIDTH
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// (a common pattern created by pmux2shiftx)
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// which is checked by ensuring that all that
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// the appropriate LSBs of B are constant zero,
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// then we can decompose LSB first instead of
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// MSB first
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localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
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if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
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_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
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_TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
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// Halve the size of $shift/$shiftx by $mux-ing A according to
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// the LSB of B, after discarding the zeroed bits
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localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
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localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
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localparam len = Y_WIDTH2 * ((entries+1)/2);
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wire [len-1:0] AA;
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wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){a_padding}}, A};
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genvar i;
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for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
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assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
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wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
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if (_TECHMAP_CELLTYPE_ == "$shift")
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$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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else
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$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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end
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else
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`endif
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begin
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localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
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localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
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integer i;
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(* force_downto *)
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reg [WIDTH-1:0] buffer;
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reg overflow;
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integer i;
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(* force_downto *)
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = 0;
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always @* begin
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overflow = 0;
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buffer = {WIDTH{extbit}};
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buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
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buffer[A_WIDTH-1:0] = A;
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if (B_WIDTH > BB_WIDTH) begin
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if (B_SIGNED) begin
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for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
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if (B[i] != B[BB_WIDTH-1])
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overflow = 1;
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end else
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overflow = |B[B_WIDTH-1:BB_WIDTH];
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if (overflow)
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buffer = {WIDTH{extbit}};
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buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
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buffer[A_WIDTH-1:0] = A;
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if (B_WIDTH > BB_WIDTH) begin
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if (B_SIGNED) begin
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for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
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if (B[i] != B[BB_WIDTH-1])
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overflow = 1;
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end else
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overflow = |B[B_WIDTH-1:BB_WIDTH];
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if (overflow)
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buffer = {WIDTH{extbit}};
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end
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for (i = BB_WIDTH-1; i >= 0; i = i-1)
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if (B[i]) begin
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if (B_SIGNED && i == BB_WIDTH-1)
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buffer = {buffer, {2**i{extbit}}};
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else if (2**i < WIDTH)
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buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{extbit}};
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end
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end
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assign Y = buffer;
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end
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endgenerate
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if (B_SIGNED && B[BB_WIDTH-1])
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buffer = {buffer, {2**(BB_WIDTH-1){extbit}}};
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for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)
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if (B[i]) begin
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if (2**i < WIDTH)
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buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{extbit}};
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end
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end
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assign Y = buffer;
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endmodule
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@ -70,8 +70,9 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 5 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-max 2 t:MISTRAL_ALUT5
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select -assert-max 5 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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@ -73,12 +73,6 @@ pmux2shiftx
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design -save gold
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design -load gold
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techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
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abc -lut 6
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select -assert-min 17 t:$lut
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design -load gold
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techmap
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abc -lut 6
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@ -91,12 +85,6 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load gold
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techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
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abc9 -lut 6
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select -assert-min 17 t:$lut
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design -load gold
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techmap
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abc9 -lut 6
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