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Merge pull request #2405 from byuccl/fix_xilinx_cells 

xilinx/cells_sim.v: Move signal declaration to before first use
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clairexen 2020-10-20 17:11:36 +02:00 committed by GitHub
parent 099d0c2a8a 8be56960a2
commit e919d0c125
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1 changed files with 2 additions and 2 deletions
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techlibs/xilinx/cells_sim.v
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@ -2335,6 +2335,8 @@ parameter integer PREG = 1;
// The multiplier.
wire signed [35:0] P_MULT;
wire signed [17:0] A_MULT;
wire signed [17:0] B_MULT;
assign P_MULT = A_MULT * B_MULT;
// The cascade output.
@ -2373,8 +2375,6 @@ always @(posedge CLK) begin
end
// The register enables.
wire signed [17:0] A_MULT;
wire signed [17:0] B_MULT;
assign A_MULT = (AREG == 1) ? A_REG : A;
assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
assign P = (PREG == 1) ? P_REG : P_MULT;