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xilinx/ice40/ecp5: zinit requires selected wires, so select them all

This commit is contained in:
Eddie Hung 2020-04-21 15:45:05 -07:00
parent b65610fb62
commit 6c34945371
3 changed files with 4 additions and 4 deletions
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2
techlibs/ecp5/synth_ecp5.cc
View File

@ -316,7 +316,7 @@ struct SynthEcp5Pass : public ScriptPass
if (!nodffe)
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
if ((abc9 && dff) || help_mode)
run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
run("opt_expr -undriven -mux_undef");
run("simplemap");

2
techlibs/ice40/synth_ice40.cc
View File

@ -362,7 +362,7 @@ struct SynthIce40Pass : public ScriptPass
run("simplemap t:$dff");
}
if ((abc9 && dff) || help_mode)
run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
run("techmap -map +/ice40/ff_map.v");
run("opt_expr -mux_undef");
run("simplemap");

4
techlibs/xilinx/synth_xilinx.cc
View File

@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_ffs", "('-abc9' only)")) {
if (abc9 || help_mode) {
if (dff || help_mode)
run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)");
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)");
run("techmap -map " + ff_map_file);
}
}
@ -608,7 +608,7 @@ struct SynthXilinxPass : public ScriptPass
if (flatten_before_abc)
run("flatten");
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {
if (lut_size != 6)
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");