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machxo2: Add FACADE_IO simulation model. More comments on models.

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William D. Jones 2020-11-21 11:58:30 -05:00 committed by Marcelina Kościelnicka
parent 1b703d3f03
commit 0364ded385
1 changed files with 25 additions and 0 deletions
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25
techlibs/machxo2/cells_sim.v
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@ -69,10 +69,12 @@ module FACADE_FF #(
endgenerate
endmodule
/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
module PFUMX (input ALUT, BLUT, C0, output Z);
assign Z = C0 ? ALUT : BLUT;
endmodule
/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
module L6MUX21 (input D0, D1, SD, output Z);
assign Z = SD ? D1 : D0;
endmodule
@ -141,6 +143,8 @@ module FACADE_SLICE #(
end
endgenerate
/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
outputs (in other words, feeds back into FACADE_SLICE). */
wire di0 = (REG0_SD == "1") ? M0 : DI0;
wire di1 = (REG0_SD == "1") ? M1 : DI1;
@ -151,3 +155,24 @@ module FACADE_SLICE #(
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
.REGMODE(REG1_REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
endmodule
module FACADE_IO #(
parameter DIR = "INPUT"
) (
inout PAD,
input I, EN,
output O
);
generate
if (DIR == "INPUT") begin
assign O = PAD;
end else if (DIR == "OUTPUT") begin
assign PAD = EN ? I : 1'bz;
end else if (DIR == "BIDIR") begin
assign PAD = EN ? I : 1'bz;
assign O = PAD;
end else begin
ERROR_UNKNOWN_IO_MODE error();
end
endgenerate
endmodule