mirror of https://github.com/YosysHQ/yosys.git
xilinx: Add some missing blackbox cells.
This commit is contained in:
Marcelina Kościelnicka
parent
5ffb676fa9
commit
f2932628fc
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@ -2023,6 +2023,105 @@ module RAM64M8 (
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end
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endmodule
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module RAM32X16DR8 (
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output DOA,
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output DOB,
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output DOC,
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output DOD,
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output DOE,
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output DOF,
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output DOG,
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output [1:0] DOH,
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input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG,
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input [4:0] ADDRH,
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input [1:0] DIA,
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input [1:0] DIB,
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input [1:0] DIC,
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input [1:0] DID,
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input [1:0] DIE,
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input [1:0] DIF,
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input [1:0] DIG,
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input [1:0] DIH,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h;
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assign DOA = mem_a[ADDRA];
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assign DOB = mem_b[ADDRB];
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assign DOC = mem_c[ADDRC];
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assign DOD = mem_d[ADDRD];
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assign DOE = mem_e[ADDRE];
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assign DOF = mem_f[ADDRF];
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assign DOG = mem_g[ADDRG];
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assign DOH = mem_h[2*ADDRH+:2];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk)
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if (WE) begin
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mem_a[2*ADDRH+:2] <= DIA;
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mem_b[2*ADDRH+:2] <= DIB;
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mem_c[2*ADDRH+:2] <= DIC;
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mem_d[2*ADDRH+:2] <= DID;
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mem_e[2*ADDRH+:2] <= DIE;
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mem_f[2*ADDRH+:2] <= DIF;
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mem_g[2*ADDRH+:2] <= DIG;
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mem_h[2*ADDRH+:2] <= DIH;
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end
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endmodule
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module RAM64X8SW (
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output [7:0] O,
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input [5:0] A,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE,
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input [2:0] WSEL
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);
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parameter [63:0] INIT_A = 64'h0000000000000000;
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parameter [63:0] INIT_B = 64'h0000000000000000;
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parameter [63:0] INIT_C = 64'h0000000000000000;
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parameter [63:0] INIT_D = 64'h0000000000000000;
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parameter [63:0] INIT_E = 64'h0000000000000000;
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parameter [63:0] INIT_F = 64'h0000000000000000;
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parameter [63:0] INIT_G = 64'h0000000000000000;
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parameter [63:0] INIT_H = 64'h0000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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reg [63:0] mem_a = INIT_A;
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reg [63:0] mem_b = INIT_B;
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reg [63:0] mem_c = INIT_C;
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reg [63:0] mem_d = INIT_D;
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reg [63:0] mem_e = INIT_E;
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reg [63:0] mem_f = INIT_F;
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reg [63:0] mem_g = INIT_G;
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reg [63:0] mem_h = INIT_H;
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assign O[7] = mem_a[A];
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assign O[6] = mem_b[A];
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assign O[5] = mem_c[A];
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assign O[4] = mem_d[A];
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assign O[3] = mem_e[A];
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assign O[2] = mem_f[A];
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assign O[1] = mem_g[A];
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assign O[0] = mem_h[A];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk)
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if (WE) begin
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case (WSEL)
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3'b111: mem_a[A] <= D;
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3'b110: mem_b[A] <= D;
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3'b101: mem_c[A] <= D;
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3'b100: mem_d[A] <= D;
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3'b011: mem_e[A] <= D;
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3'b010: mem_f[A] <= D;
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3'b001: mem_g[A] <= D;
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3'b000: mem_h[A] <= D;
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endcase
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end
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endmodule
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// ROM.
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module ROM16X1 (
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@ -57,6 +57,8 @@ CELLS = [
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# Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM32X16DR8', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAM64X8SW', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('ROM16X1'),
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# Cell('ROM32X1'),
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# Cell('ROM64X1'),
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@ -243,12 +245,12 @@ CELLS = [
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'CLKDIVP': ['clkbuf_sink'],
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}),
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Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
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Cell('PHASER_IN'),
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Cell('PHASER_IN_PHY'),
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Cell('PHASER_OUT'),
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Cell('PHASER_OUT_PHY'),
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Cell('PHASER_REF'),
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Cell('PHY_CONTROL'),
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Cell('PHASER_IN', keep=True),
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Cell('PHASER_IN_PHY', keep=True),
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Cell('PHASER_OUT', keep=True),
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Cell('PHASER_OUT_PHY', keep=True),
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Cell('PHASER_REF', keep=True),
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Cell('PHY_CONTROL', keep=True),
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# Ultrascale.
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Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
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Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
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@ -262,7 +264,7 @@ CELLS = [
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}),
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Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
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Cell('BITSLICE_CONTROL', keep=True),
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Cell('RIU_OR'),
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Cell('RIU_OR', keep=True),
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Cell('RX_BITSLICE'),
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Cell('RXTX_BITSLICE'),
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Cell('TX_BITSLICE'),
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@ -327,7 +329,7 @@ CELLS = [
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Cell('PULLUP'),
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# Misc.
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Cell('DCIRESET', keep=True),
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Cell('HPIO_VREF'), # Ultrascale
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Cell('HPIO_VREF', keep=True), # Ultrascale
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# Clock buffers (global).
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# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
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@ -456,6 +458,7 @@ CELLS = [
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Cell('FRAME_ECC_VIRTEX6'),
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Cell('FRAME_ECCE2'), # Series 7
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Cell('FRAME_ECCE3'), # Ultrascale
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Cell('FRAME_ECCE4'), # Ultrascale+
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# AXSS command access.
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Cell('USR_ACCESS_VIRTEX4'),
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Cell('USR_ACCESS_VIRTEX5'),
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@ -470,10 +473,10 @@ CELLS = [
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Cell('EFUSE_USR'),
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# ADC.
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Cell('SYSMON'), # Virtex 5/6
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Cell('XADC'), # Series 7
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Cell('SYSMONE1'), # Ultrascale
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Cell('SYSMONE4'), # Ultrascale+
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Cell('SYSMON', keep=True), # Virtex 5/6
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Cell('XADC', keep=True), # Series 7
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Cell('SYSMONE1', keep=True), # Ultrascale
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Cell('SYSMONE4', keep=True), # Ultrascale+
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# Gigabit transceivers.
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# Spartan 6.
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@ -507,18 +510,30 @@ CELLS = [
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# Ultrascale.
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Cell('GTHE3_CHANNEL'),
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Cell('GTHE3_COMMON'),
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Cell('GTHE4_CHANNEL'),
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Cell('GTHE4_COMMON'),
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Cell('GTYE3_CHANNEL'),
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Cell('GTYE3_COMMON'),
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Cell('GTYE4_CHANNEL'),
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Cell('GTYE4_COMMON'),
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Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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# Ultrascale+.
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Cell('GTHE4_CHANNEL'),
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Cell('GTHE4_COMMON'),
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Cell('GTYE4_CHANNEL'),
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Cell('GTYE4_COMMON'),
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Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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# Ultrascale+ GTM.
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Cell('GTM_DUAL'), # not in the libraries guide
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Cell('IBUFDS_GTM', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('OBUFDS_GTM', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFDS_GTM_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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# High-speed ADC/DAC.
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Cell('HSDAC'), # not in libraries guide
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Cell('HSADC'), # not in libraries guide
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Cell('RFDAC'), # not in libraries guide
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Cell('RFADC'), # not in libraries guide
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# PCIE IP.
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Cell('PCIE_A1'), # Spartan 6
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@ -528,6 +543,7 @@ CELLS = [
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Cell('PCIE_3_0'), # Series 7
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Cell('PCIE_3_1'), # Ultrascale
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Cell('PCIE40E4'), # Ultrascale+
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Cell('PCIE4CE4'), # Ultrascale+ v2 (not in the libraries guide)
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# Ethernet IP.
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Cell('EMAC'), # Virtex 4
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@ -536,17 +552,29 @@ CELLS = [
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Cell('CMAC'), # Ultrascale
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Cell('CMACE4'), # Ultrsacale+
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# Hard memory controllers.
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Cell('MCB'), # Spartan 6 Memory Controller Block
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Cell('HBM_REF_CLK', keep=True), # not in liraries guide
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# not sure how the following relate to the hw
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Cell('HBM_SNGLBLI_INTF_APB', keep=True), # not in liraries guide
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Cell('HBM_SNGLBLI_INTF_AXI', keep=True), # not in liraries guide
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Cell('HBM_ONE_STACK_INTF', keep=True), # not in liraries guide
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Cell('HBM_TWO_STACK_INTF', keep=True), # not in liraries guide
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# PowerPC.
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# TODO PPC405 (Virtex 2)
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Cell('PPC405_ADV'), # Virtex 4
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Cell('PPC440'), # Virtex 5
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# ARM.
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Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System (not in libraries guide).
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Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System (not in libraries guide).
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# Misc hard IP.
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Cell('MCB'), # Spartan 6 Memory Controller Block
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Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System.
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Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System.
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Cell('ILKN'), # Ultrascale Interlaken
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Cell('ILKNE4'), # Ultrascale+ Interlaken
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Cell('VCU', keep=True), # Zynq MPSoC Video Codec Unit (not in libraries guide).
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Cell('FE'), # Zynq RFSoC Forward Error Correction (not in libraries guide).
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]
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@ -559,100 +587,101 @@ class State(Enum):
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def xtract_cell_decl(cell, dirs, outf):
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for dir in dirs:
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fname = os.path.join(dir, cell.name + '.v')
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try:
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with open(fname) as f:
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state = State.OUTSIDE
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found = False
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# Probably the most horrible Verilog "parser" ever written.
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module_ports = []
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invertible_ports = set()
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for l in f:
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l = l.partition('//')[0]
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l = l.strip()
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if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
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if found:
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print('Multiple modules in {}.'.format(fname))
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sys.exit(1)
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elif state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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found = True
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state = State.IN_MODULE
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if cell.keep:
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outf.write('(* keep *)\n')
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outf.write('module {} (...);\n'.format(cell.name))
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elif l.startswith('module '):
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if state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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state = State.IN_OTHER_MODULE
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elif l.startswith('task '):
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if state == State.IN_MODULE:
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state = State.IN_TASK
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elif l.startswith('function '):
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if state == State.IN_MODULE:
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state = State.IN_FUNCTION
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elif l == 'endtask':
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if state == State.IN_TASK:
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for ext in ['.v', '.sv']:
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fname = os.path.join(dir, cell.name + ext)
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try:
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with open(fname) as f:
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state = State.OUTSIDE
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found = False
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# Probably the most horrible Verilog "parser" ever written.
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module_ports = []
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invertible_ports = set()
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for l in f:
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l = l.partition('//')[0]
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l = l.strip()
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if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
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if found:
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print('Multiple modules in {}.'.format(fname))
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sys.exit(1)
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elif state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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found = True
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state = State.IN_MODULE
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elif l == 'endfunction':
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if state == State.IN_FUNCTION:
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state = State.IN_MODULE
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elif l == 'endmodule':
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if state == State.IN_MODULE:
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for kind, rng, port in module_ports:
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for attr in cell.port_attrs.get(port, []):
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outf.write(' (* {} *)\n'.format(attr))
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if port in invertible_ports:
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outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
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if rng is None:
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outf.write(' {} {};\n'.format(kind, port))
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if cell.keep:
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outf.write('(* keep *)\n')
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outf.write('module {} (...);\n'.format(cell.name))
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elif l.startswith('module '):
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if state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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state = State.IN_OTHER_MODULE
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elif l.startswith('task '):
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if state == State.IN_MODULE:
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state = State.IN_TASK
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elif l.startswith('function '):
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if state == State.IN_MODULE:
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state = State.IN_FUNCTION
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elif l == 'endtask':
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if state == State.IN_TASK:
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state = State.IN_MODULE
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elif l == 'endfunction':
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if state == State.IN_FUNCTION:
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state = State.IN_MODULE
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elif l == 'endmodule':
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if state == State.IN_MODULE:
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for kind, rng, port in module_ports:
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for attr in cell.port_attrs.get(port, []):
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outf.write(' (* {} *)\n'.format(attr))
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if port in invertible_ports:
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outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
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if rng is None:
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outf.write(' {} {};\n'.format(kind, port))
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else:
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outf.write(' {} {} {};\n'.format(kind, rng, port))
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outf.write(l + '\n')
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outf.write('\n')
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elif state != State.IN_OTHER_MODULE:
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print('endmodule in weird place in {}.'.format(cell.name, fname))
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sys.exit(1)
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state = State.OUTSIDE
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elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
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if l.endswith((';', ',')):
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l = l[:-1]
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if ';' in l:
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print('Weird port line in {} [{}].'.format(fname, l))
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sys.exit(1)
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kind, _, ports = l.partition(' ')
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for port in ports.split(','):
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port = port.strip()
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if port.startswith('['):
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rng, port = port.split()
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else:
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outf.write(' {} {} {};\n'.format(kind, rng, port))
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outf.write(l + '\n')
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outf.write('\n')
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elif state != State.IN_OTHER_MODULE:
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print('endmodule in weird place in {}.'.format(cell.name, fname))
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sys.exit(1)
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state = State.OUTSIDE
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elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
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if l.endswith((';', ',')):
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l = l[:-1]
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if ';' in l:
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print('Weird port line in {} [{}].'.format(fname, l))
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sys.exit(1)
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kind, _, ports = l.partition(' ')
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for port in ports.split(','):
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port = port.strip()
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if port.startswith('['):
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rng, port = port.split()
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else:
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rng = None
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module_ports.append((kind, rng, port))
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elif l.startswith('parameter ') and state == State.IN_MODULE:
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if 'UNPLACED' in l:
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continue
|
||||
if l.endswith((';', ',')):
|
||||
l = l[:-1]
|
||||
while ' ' in l:
|
||||
l = l.replace(' ', ' ')
|
||||
if ';' in l:
|
||||
print('Weird parameter line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
outf.write(' {};\n'.format(l))
|
||||
match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
|
||||
if match:
|
||||
invertible_ports.add(match[1])
|
||||
if state != State.OUTSIDE:
|
||||
print('endmodule not found in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
if not found:
|
||||
print('Cannot find module {} in {}.'.format(cell.name, fname))
|
||||
sys.exit(1)
|
||||
return
|
||||
except FileNotFoundError:
|
||||
continue
|
||||
rng = None
|
||||
module_ports.append((kind, rng, port))
|
||||
elif l.startswith('parameter ') and state == State.IN_MODULE:
|
||||
if 'UNPLACED' in l:
|
||||
continue
|
||||
if l.endswith((';', ',')):
|
||||
l = l[:-1]
|
||||
while ' ' in l:
|
||||
l = l.replace(' ', ' ')
|
||||
if ';' in l:
|
||||
print('Weird parameter line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
outf.write(' {};\n'.format(l))
|
||||
match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
|
||||
if match:
|
||||
invertible_ports.add(match[1])
|
||||
if state != State.OUTSIDE:
|
||||
print('endmodule not found in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
if not found:
|
||||
print('Cannot find module {} in {}.'.format(cell.name, fname))
|
||||
sys.exit(1)
|
||||
return
|
||||
except FileNotFoundError:
|
||||
continue
|
||||
print('Cannot find {}.'.format(cell.name))
|
||||
sys.exit(1)
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue