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ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v

This commit is contained in:
Eddie Hung 2020-05-13 14:16:42 -07:00
parent 39759d5f0e
commit fdc340db8e
4 changed files with 3 additions and 43 deletions
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3
techlibs/ecp5/Makefile.inc
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@ -23,9 +23,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk

27
techlibs/ecp5/abc9_map.v
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@ -1,27 +0,0 @@
// ---------------------------------------
// Attach a (combinatorial) black-box onto the output
// of this LUTRAM primitive to capture its
// asynchronous read behaviour
module TRELLIS_DPR16X4 (
(* techmap_autopurge *) input [3:0] DI,
(* techmap_autopurge *) input [3:0] WAD,
(* techmap_autopurge *) input WRE,
(* techmap_autopurge *) input WCK,
(* techmap_autopurge *) input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
wire [3:0] $DO;
TRELLIS_DPR16X4 #(
.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
) _TECHMAP_REPLACE_ (
.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
.RAD(RAD), .DO($DO)
);
$__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO));
endmodule

5
techlibs/ecp5/abc9_unmap.v
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@ -1,5 +0,0 @@
// ---------------------------------------
module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
assign DO = $DO;
endmodule

11
techlibs/ecp5/synth_ecp5.cc
View File

@ -328,14 +328,10 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("map_luts"))
{
if (abc2 || help_mode) {
if (abc2 || help_mode)
run("abc", " (only if -abc2)");
}
std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
if (abc9)
techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
if (!techmap_args.empty())
run("techmap " + techmap_args);
if (asyncprld || help_mode)
run("techmap -map +/ecp5/latches_map.v", "(only if -asyncprld)");
if (abc9) {
run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
@ -352,7 +348,6 @@ struct SynthEcp5Pass : public ScriptPass
if (dff)
abc9_opts += " -dff";
run("abc9" + abc9_opts);
run("techmap -map +/ecp5/abc9_unmap.v");
} else {
std::string abc_args = " -dress";
if (nowidelut)