mirror of https://github.com/YosysHQ/yosys.git
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
This commit is contained in:
Eddie Hung
parent
577545488a
commit
46a89d7264
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@ -18,9 +18,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
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EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
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.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
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@ -1,36 +0,0 @@
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# NB: Box inputs/outputs must each be in the same order
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# as their corresponding module definition
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# (with exceptions detailed below)
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# Box 1 : CCU2C (2xCARRY + 2xLUT4)
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# (Exception: carry chain input/output must be the
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# last input and output and the entire bus has been
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# moved there overriding the otherwise
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# alphabetical ordering)
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# name ID w/b ins outs
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CCU2C 1 1 9 3
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#A0 B0 C0 D0 A1 B1 C1 D1 CIN
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379 379 275 141 - - - - 257 # S0
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630 630 526 392 379 379 275 141 273 # S1
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516 516 412 278 516 516 412 278 43 # COUT
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# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
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# name ID w/b ins outs
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$__ABC9_DPR16X4_COMB 2 0 8 4
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#$DO0 $DO1 $DO2 $DO3 RAD0 RAD1 RAD2 RAD3
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0 0 0 0 141 379 275 379 # DO0
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0 0 0 0 141 379 275 379 # DO1
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0 0 0 0 141 379 275 379 # DO2
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0 0 0 0 141 379 275 379 # DO3
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# Box 3 : PFUMX (MUX2)
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# name ID w/b ins outs
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PFUMX 3 1 3 1
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#ALUT BLUT C0
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98 98 151 # Z
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# Box 4 : L6MUX21 (MUX2)
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# name ID w/b ins outs
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L6MUX21 4 1 3 1
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#D0 D1 SD
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140 141 148 # Z
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@ -1,25 +0,0 @@
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# ECP5-5G LUT library for ABC
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# Note that ECP5 architecture assigns difference
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# in LUT input delay to interconnect, so this is
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# considered too
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# Simple LUTs
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# area D C B A
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1 1 141
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2 1 141 275
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3 1 141 275 379
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4 1 141 275 379 379
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# LUT5 = 2x LUT4 + PFUMX
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# area M0 D C B A
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5 2 151 239 373 477 477
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# LUT6 = 2x LUT5 + MUX2
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# area M1 M0 D C B A
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6 4 148 292 380 514 618 618
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# LUT7 = 2x LUT6 + MUX2
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# area M2 M1 M0 D C B A
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7 8 148 289 433 521 655 759 759
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@ -1,12 +0,0 @@
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# ECP5-5G LUT library for ABC
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# Note that ECP5 architecture assigns difference
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# in LUT input delay to interconnect, so this is
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# considered too
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# Simple LUTs
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# area D C B A
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1 1 141
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2 1 141 275
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3 1 141 275 379
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4 1 141 275 379 379
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@ -1,5 +1,12 @@
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// ---------------------------------------
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(* abc9_box_id=2 *)
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(* abc9_box *)
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module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
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specify
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($DO => DO) = 0;
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(RAD[0] *> DO) = 141;
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(RAD[1] *> DO) = 379;
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(RAD[2] *> DO) = 275;
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(RAD[3] *> DO) = 379;
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endspecify
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endmodule
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@ -1,22 +1,96 @@
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// ---------------------------------------
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(* lib_whitebox *)
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(* abc9_lut=1, lib_whitebox *)
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module LUT4(input A, B, C, D, output Z);
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parameter [15:0] INIT = 16'h0000;
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wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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specify
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(A => Z) = 141;
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(B => Z) = 275;
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(C => Z) = 379;
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(D => Z) = 379;
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endspecify
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endmodule
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(* abc9_lut=1 *)
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module \$__ABC9_LUT1 (input A, output Z);
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specify
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(A => Z) = 141;
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endspecify
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endmodule
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(* abc9_lut=1 *)
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module \$__ABC9_LUT2 (input A, B, output Z);
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specify
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(A => Z) = 141;
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(B => Z) = 275;
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endspecify
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endmodule
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(* abc9_lut=1 *)
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module \$__ABC9_LUT3 (input A, B, C, output Z);
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specify
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(A => Z) = 141;
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(B => Z) = 275;
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(C => Z) = 379;
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endspecify
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endmodule
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// LUT5 = 2x LUT4 + PFUMX
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(* abc9_lut=2 *)
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module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
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specify
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(M0 => Z) = 151;
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(D => Z) = 239;
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(C => Z) = 373;
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(B => Z) = 477;
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(A => Z) = 477;
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endspecify
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endmodule
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// LUT6 = 2x LUT5 + MUX2
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(* abc9_lut=4 *)
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module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
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specify
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(M1 => Z) = 148;
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(M0 => Z) = 292;
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(D => Z) = 380;
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(C => Z) = 514;
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(B => Z) = 618;
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(A => Z) = 618;
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endspecify
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endmodule
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// LUT7 = 2x LUT6 + MUX2
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(* abc9_lut=8 *)
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module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
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specify
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(M2 => Z) = 148;
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(M1 => Z) = 289;
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(M0 => Z) = 433;
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(D => Z) = 521;
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(C => Z) = 655;
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(B => Z) = 759;
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(A => Z) = 759;
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endspecify
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endmodule
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// ---------------------------------------
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(* abc9_box_id=4, lib_whitebox *)
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(* abc9_box, lib_whitebox *)
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module L6MUX21 (input D0, D1, SD, output Z);
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assign Z = SD ? D1 : D0;
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specify
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(D0 => Z) = 140;
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(D1 => Z) = 141;
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(SD => Z) = 148;
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endspecify
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endmodule
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// ---------------------------------------
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(* abc9_box_id=1, lib_whitebox *)
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(* abc9_box, lib_whitebox *)
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module CCU2C(
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(* abc9_carry *)
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input CIN,
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@ -50,6 +124,31 @@ module CCU2C(
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wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
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assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
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specify
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(A0 => S0) = 379;
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(B0 => S0) = 379;
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(C0 => S0) = 275;
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(D0 => S0) = 141;
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(CIN => S0) = 257;
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(A0 => S1) = 630;
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(B0 => S1) = 630;
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(C0 => S1) = 526;
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(D0 => S1) = 392;
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(A1 => S1) = 379;
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(B1 => S1) = 379;
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(C1 => S1) = 275;
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(D1 => S1) = 141;
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(CIN => S1) = 273;
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(A0 => COUT) = 516;
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(B0 => COUT) = 516;
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(C0 => COUT) = 412;
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(D0 => COUT) = 278;
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(A1 => COUT) = 516;
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(B1 => COUT) = 516;
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(C1 => COUT) = 412;
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(D1 => COUT) = 278;
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(CIN => COUT) = 43;
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endspecify
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endmodule
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// ---------------------------------------
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@ -94,9 +193,14 @@ module TRELLIS_RAM16X2 (
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endmodule
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// ---------------------------------------
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(* abc9_box_id=3, lib_whitebox *)
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(* abc9_box, lib_whitebox *)
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module PFUMX (input ALUT, BLUT, C0, output Z);
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assign Z = C0 ? ALUT : BLUT;
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specify
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(ALUT => Z) = 98;
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(BLUT => Z) = 98;
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(C0 => Z) = 151;
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endspecify
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endmodule
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// ---------------------------------------
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@ -106,7 +210,6 @@ module TRELLIS_DPR16X4 (
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input WRE,
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input WCK,
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input [3:0] RAD,
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/* (* abc9_arrival=<TODO> *) */
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output [3:0] DO
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);
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parameter WCKMUX = "WCK";
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@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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@ -322,11 +322,11 @@ struct SynthEcp5Pass : public ScriptPass
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run("techmap " + techmap_args);
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if (abc9) {
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run("read_verilog -icells -lib +/ecp5/abc9_model.v");
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run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
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if (nowidelut)
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run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
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run("abc9 -maxlut 4 -W 200");
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else
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run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
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run("abc9 -W 200");
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run("techmap -map +/ecp5/abc9_unmap.v");
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} else {
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if (nowidelut)
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