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intel_alm: increase abc9 -W
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@ -258,7 +258,7 @@ struct SynthIntelALMPass : public ScriptPass {
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if (check_label("map_luts")) {
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run("techmap -map +/intel_alm/common/abc9_map.v");
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run(stringf("abc9 %s -maxlut 6 -W 200", help_mode ? "[-dff]" : dff ? "-dff" : ""));
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run(stringf("abc9 %s -maxlut 6 -W 600", help_mode ? "[-dff]" : dff ? "-dff" : ""));
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run("techmap -map +/intel_alm/common/abc9_unmap.v");
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run("techmap -map +/intel_alm/common/alm_map.v");
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run("opt -fast");
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@ -47,9 +47,9 @@ proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 3 t:MISTRAL_ALUT5
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select -assert-count 1 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 2 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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@ -69,9 +69,9 @@ proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 2 t:MISTRAL_ALUT5
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select -assert-count 4 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 5 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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