mirror of https://github.com/YosysHQ/yosys.git
synth_*: no need to explicitly read +/abc9_model.v
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@ -338,7 +338,7 @@ struct SynthEcp5Pass : public ScriptPass
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run("techmap " + techmap_args);
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if (abc9) {
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run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
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run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
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std::string abc9_opts;
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if (nowidelut)
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abc9_opts += " -maxlut 4";
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@ -387,7 +387,7 @@ struct SynthIce40Pass : public ScriptPass
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}
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if (!noabc) {
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if (abc9) {
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run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
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run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
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std::string abc9_opts;
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std::string k = "synth_ice40.abc9.W";
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if (active_design && active_design->scratchpad.count(k))
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@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass {
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}
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if (check_label("map_luts")) {
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run("read_verilog -icells -specify -lib +/abc9_model.v");
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run("abc9 -maxlut 6 -W 200");
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run("techmap -map +/intel_alm/common/alm_map.v");
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run("opt -fast");
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@ -616,7 +616,7 @@ struct SynthXilinxPass : public ScriptPass
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log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
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"will use timing for 'xc7' instead.\n", family.c_str());
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run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
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run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
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run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
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std::string abc9_opts;
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std::string k = "synth_xilinx.abc9.W";
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if (active_design && active_design->scratchpad.count(k))
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