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ice40: Fix typos in SPRAM ABC9 timing specs 

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2020-03-20 22:19:55 +01:00
parent 9b982e929c
commit c15ce5a73e
1 changed files with 2 additions and 2 deletions
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4
techlibs/ice40/cells_sim.v
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@ -2382,9 +2382,9 @@ module SB_SPRAM256KA (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
//$setup(negedge STANDBY, posedge CLOCK, 1715);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
$setup(WREN, posedge CLK, 289);
$setup(WREN, posedge CLOCK, 289);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
(posedge RCLK => (DATAOUT : 16'bx)) = 1821;
(posedge CLOCK => (DATAOUT : 16'bx)) = 1821;
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
(posedge SLEEP => (DATAOUT : 16'b0)) = 1099;
endspecify