mirror of https://github.com/YosysHQ/yosys.git
synth_intel: Remove incomplete Arria 10 GX support.
The techmap rules for this target do not work in the first place (note lack of >2-input LUT mappings), and if proper support is ever added, it'd be better placed in the synth_intel_alm backend.
This commit is contained in:
Marcelina Kościelnicka
parent
034b9ec716
commit
082cbcb4c7
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@ -8,7 +8,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_
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$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
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# Add the cell models and mappings for the VQM backend
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families := max10 arria10gx cyclone10lp cycloneiv cycloneive
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families := max10 cyclone10lp cycloneiv cycloneive
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$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
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$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
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#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
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@ -1,71 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// NOTE: This is still WIP.
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(* techmap_celltype = "$alu" *)
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module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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//output [Y_WIDTH-1:0] CO;
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output CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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//wire [Y_WIDTH:0] C = {CO, CI};
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wire [Y_WIDTH+1:0] COx;
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wire [Y_WIDTH+1:0] C = {COx, CI};
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/* Start implementation */
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(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
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if(i==Y_WIDTH-1) begin
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(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
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assign CO = COx[Y_WIDTH];
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end
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else
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fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
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end: slice
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endgenerate
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/* End implementation */
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assign X = AA ^ BB;
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endmodule
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@ -1,54 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// Input buffer map
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module \$__inpad (input I, output O);
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twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
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endmodule
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// Output buffer map
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module \$__outpad (input I, output O);
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twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
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endmodule
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// LUT Map
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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end else
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if (WIDTH == 2) begin
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twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
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end /*else
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if(WIDTH == 3) begin
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fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
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end else
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if(WIDTH == 4) begin
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fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
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end*/ else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule //
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@ -1,59 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Arria 10 GX devices Input Buffer Primitive */
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module twentynm_io_ibuf (output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // twentynm_io_ibuf
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/* Altera Arria 10 GX devices Output Buffer Primitive */
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module twentynm_io_obuf (output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // twentynm_io_obuf
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/* Altera Arria 10 GX LUT Primitive */
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module twentynm_lcell_comb (output combout, cout, sumout,
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input dataa, datab, datac, datad,
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input datae, dataf, datag, cin,
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input sharein);
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parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "twentynm_lcell_comb";
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parameter shared_arith = "off";
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parameter extended_lut = "off";
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// TODO: This is still WIP
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initial begin
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$display("Simulation model is still under investigation\n");
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end
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endmodule // twentynm_lcell_comb
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@ -36,11 +36,11 @@ struct SynthIntelPass : public ScriptPass {
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log("\n");
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log("This command runs synthesis for Intel FPGAs.\n");
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log("\n");
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log(" -family <max10 | arria10gx | cyclone10lp | cycloneiv | cycloneive>\n");
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log(" -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n");
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log(" generate the synthesis netlist for the specified family.\n");
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log(" MAX10 is the default target if no family argument specified.\n");
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log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
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log(" Arria 10 GX devices are experimental.\n");
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log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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@ -152,7 +152,6 @@ struct SynthIntelPass : public ScriptPass {
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log_cmd_error("Cyclone V synthesis has been moved to synth_intel_alm.\n");
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if (family_opt != "max10" &&
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family_opt != "arria10gx" &&
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family_opt != "cycloneiv" &&
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family_opt != "cycloneive" &&
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family_opt != "cyclone10lp")
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@ -219,10 +218,7 @@ struct SynthIntelPass : public ScriptPass {
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}
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if (check_label("map_luts")) {
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if (family_opt == "arria10gx")
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run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
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else
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run("abc -lut 4" + string(retime ? " -dff" : ""));
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run("abc -lut 4" + string(retime ? " -dff" : ""));
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run("clean");
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}
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