mirror of https://github.com/YosysHQ/yosys.git
ice40: move over to specify blocks for -abc9
This commit is contained in:
Eddie Hung
parent
a85c55113f
commit
fb60d82971
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@ -29,12 +29,6 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut))
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$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
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$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
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@ -1,17 +0,0 @@
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# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
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# NB: Box inputs/outputs must each be in the same order
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# as their corresponding module definition
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# (with exceptions detailed below)
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# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
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# SB_LUT4+SB_CARRY)
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# (Exception: carry chain input/output must be the
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# last input and output and the entire bus has been
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# moved there overriding the otherwise
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# alphabetical ordering)
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# name ID w/b ins outs
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$__ICE40_CARRY_WRAPPER 1 1 5 2
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#A B I0 I3 CI
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400 379 449 316 316 # O
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259 231 - - 126 # CO
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@ -1,6 +0,0 @@
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# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
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# I3 I2 I1 I0
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1 1 316
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2 1 316 379
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3 1 316 379 400
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4 1 316 379 400 449
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@ -1,17 +0,0 @@
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# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
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# NB: Box inputs/outputs must each be in the same order
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# as their corresponding module definition
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# (with exceptions detailed below)
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# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
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# SB_LUT4+SB_CARRY)
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# (Exception: carry chain input/output must be the
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# last input and output and the entire bus has been
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# moved there overriding the otherwise
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# alphabetical ordering)
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# name ID w/b ins outs
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$__ICE40_CARRY_WRAPPER 1 1 5 2
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#A B I0 I3 CI
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589 558 661 465 465 # O
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675 609 - - 186 # CO
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@ -1,6 +0,0 @@
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# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
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# I3 I2 I1 I0
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1 1 465
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2 1 465 558
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3 1 465 558 589
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4 1 465 558 589 661
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@ -1,4 +1,4 @@
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(* abc9_box_id = 1, lib_whitebox *)
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(* abc9_box, lib_whitebox *)
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module \$__ICE40_CARRY_WRAPPER (
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(* abc9_carry *)
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output CO,
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@ -26,4 +26,61 @@ module \$__ICE40_CARRY_WRAPPER (
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.I3(I3_OR_CI),
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.O(O)
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);
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`ifdef ICE40_HX
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specify
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
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(CI => O) = (126, 105);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
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(I0 => O) = (449, 386);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
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(A => CO) = (259, 245);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
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(A => O) = (400, 379);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
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(B => CO) = (231, 133);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
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(B => O) = (379, 351);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
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(I3 => O) = (316, 288);
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(CI => O) = (316, 288);
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endspecify
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`endif
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`ifdef ICE40_LP
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specify
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
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(CI => O) = (186, 155);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
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(I0 => O) = (662, 569);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
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(A => CO) = (382, 362);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
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(A => O) = (589, 558);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
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(B => CO) = (341, 196);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
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(B => O) = (558, 517);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
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(I3 => O) = (465, 423);
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(CI => O) = (465, 423);
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endspecify
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`endif
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`ifdef ICE40_U
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specify
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
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(CI => O) = (278, 278);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
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(I0 => O) = (1245, 1285);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
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(A => CO) = (675, 662);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
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(A => O) = (1179, 1232);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
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(B => CO) = (609, 358);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
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(B => O) = (1179, 1205);
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// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
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(I3 => O) = (861, 874);
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(CI => O) = (861, 874);
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endspecify
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`endif
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endmodule
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@ -1,17 +0,0 @@
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# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
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# NB: Box inputs/outputs must each be in the same order
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# as their corresponding module definition
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# (with exceptions detailed below)
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# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
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# SB_LUT4+SB_CARRY)
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# (Exception: carry chain input/output must be the
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# last input and output and the entire bus has been
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# moved there overriding the otherwise
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# alphabetical ordering)
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# name ID w/b ins outs
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$__ICE40_CARRY_WRAPPER 1 1 5 2
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#A B I0 I3 CI
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1231 1205 1285 874 874 # O
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675 609 - - 278 # CO
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@ -1,6 +0,0 @@
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# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
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# I3 I2 I1 I0
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1 1 874
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2 1 874 1205
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3 1 874 1205 1231
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4 1 874 1205 1231 1285
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File diff suppressed because it is too large
Load Diff
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@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
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define = "-D ICE40_U";
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else
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define = "-D ICE40_HX";
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run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
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run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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run("proc");
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}
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@ -352,7 +352,7 @@ struct SynthIce40Pass : public ScriptPass
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}
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if (!noabc) {
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if (abc9) {
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run("read_verilog -icells -lib +/ice40/abc9_model.v");
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run("read_verilog -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
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int wire_delay;
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if (device_opt == "lp")
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wire_delay = 400;
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@ -360,7 +360,7 @@ struct SynthIce40Pass : public ScriptPass
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wire_delay = 750;
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else
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wire_delay = 250;
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run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
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run(stringf("abc9 -W %d", wire_delay, device_opt.c_str(), device_opt.c_str()));
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}
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else
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run("abc -dress -lut 4", "(skip if -noabc)");
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