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coolrunner2: Attempt to give wires/cells more meaningful names

This commit is contained in:
R. Ou 2020-03-02 01:40:57 -08:00
parent b9c98e0100
commit 7932672fc2
2 changed files with 66 additions and 23 deletions
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65
techlibs/coolrunner2/coolrunner2_fixup.cc
View File

@ -23,44 +23,66 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire)
RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cellname)
{
auto outwire = module->addWire(NEW_ID);
RTLIL::Wire *outwire = nullptr;
if (inwire == SigBit(true))
{
// Constant 1
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
outwire = module->addWire(
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", true);
xor_cell->setPort("\\OUT", outwire);
}
else if (inwire == SigBit(false))
{
// Constant 0
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
outwire = module->addWire(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
}
else if (inwire == SigBit(RTLIL::State::Sx))
{
// x; treat as 0
log_warning("While buffering, changing x to 0 on wire %s\n", outwire->name.c_str());
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
log_warning("While buffering, changing x to 0 into cell %s\n", cellname);
outwire = module->addWire(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
}
else
{
auto and_to_xor_wire = module->addWire(NEW_ID);
auto inwire_name = inwire.wire->name.c_str();
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
outwire = module->addWire(
module->uniquify(stringf("$xc2fix$%s_BUF_XOR_OUT", inwire_name)));
auto and_to_xor_wire = module->addWire(
module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name)));
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", and_to_xor_wire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", outwire);
@ -71,9 +93,14 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire)
RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
{
auto outwire = module->addWire(NEW_ID);
auto inwire_name = inwire.wire->name.c_str();
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
auto outwire = module->addWire(
module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name)));
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", outwire);
@ -273,7 +300,7 @@ struct Coolrunner2FixupPass : public Pass {
{
log("Buffering input to \"%s\"\n", cell->name.c_str());
auto xor_to_ff_wire = makexorbuffer(module, input);
auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire);
@ -364,7 +391,7 @@ struct Coolrunner2FixupPass : public Pass {
{
log("Buffering input to \"%s\"\n", cell->name.c_str());
auto xor_to_io_wire = makexorbuffer(module, input);
auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
cell->setPort("\\I", xor_to_io_wire);
}
@ -425,8 +452,10 @@ struct Coolrunner2FixupPass : public Pass {
cell->name.c_str(),
cell->type.c_str());
auto new_xor_cell = module->addCell(NEW_ID, xor_cell);
auto new_wire = module->addWire(NEW_ID);
auto new_xor_cell = module->addCell(
module->uniquify(xor_cell->name), xor_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_xor_cell->setPort("\\OUT", new_wire);
cell->setPort(conn.first, new_wire);
}
@ -471,8 +500,10 @@ struct Coolrunner2FixupPass : public Pass {
cell->name.c_str(),
cell->type.c_str());
auto new_or_cell = module->addCell(NEW_ID, or_cell);
auto new_wire = module->addWire(NEW_ID);
auto new_or_cell = module->addCell(
module->uniquify(or_cell->name), or_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_or_cell->setPort("\\OUT", new_wire);
cell->setPort(conn.first, new_wire);
}

24
techlibs/coolrunner2/coolrunner2_sop.cc
View File

@ -94,6 +94,8 @@ struct Coolrunner2SopPass : public Pass {
auto sop_width = cell->getParam("\\WIDTH").as_int();
auto sop_table = cell->getParam("\\TABLE");
auto sop_output_wire_name = sop_output.wire->name.c_str();
// Check for a $_NOT_ at the output
bool has_invert = false;
if (not_cells.count(sop_output))
@ -115,7 +117,8 @@ struct Coolrunner2SopPass : public Pass {
pool<SigBit> intermed_wires;
for (int i = 0; i < sop_depth; i++) {
// Wire for the output
auto and_out = module->addWire(NEW_ID);
auto and_out = module->addWire(
module->uniquify(stringf("$xc2sop$%s_AND%d_OUT", sop_output_wire_name, i)));
intermed_wires.insert(and_out);
// Signals for the inputs
@ -134,7 +137,9 @@ struct Coolrunner2SopPass : public Pass {
}
// Construct the cell
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
and_cell->setPort("\\OUT", and_out);
@ -145,7 +150,9 @@ struct Coolrunner2SopPass : public Pass {
if (sop_depth == 1)
{
// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
xor_cell->setPort("\\OUT", sop_output);
@ -190,16 +197,21 @@ struct Coolrunner2SopPass : public Pass {
else
{
// Wire from OR to XOR
auto or_to_xor_wire = module->addWire(NEW_ID);
auto or_to_xor_wire = module->addWire(
module->uniquify(stringf("$xc2sop$%s_OR_OUT", sop_output_wire_name)));
// Construct the OR cell
auto or_cell = module->addCell(NEW_ID, "\\ORTERM");
auto or_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
"\\ORTERM");
or_cell->setParam("\\WIDTH", sop_depth);
or_cell->setPort("\\IN", intermed_wires);
or_cell->setPort("\\OUT", or_to_xor_wire);
// Construct the XOR cell
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output);