mirror of https://github.com/YosysHQ/yosys.git
coolrunner2: Fix invalid multiple fanouts of XOR/OR gates
In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule
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@ -386,6 +386,102 @@ struct Coolrunner2FixupPass : public Pass {
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}
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}
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}
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// Now we have to fix up some cases where shared logic can
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// cause XORs to have multiple fanouts to something other than
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// pterms (which is not ok)
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// Find all the XOR outputs
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dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\MACROCELL_XOR")
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{
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auto output = sigmap(cell->getPort("\\OUT")[0]);
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xor_out_to_xor_cell[output] = cell;
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}
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}
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// Find all of the sinks for each output from an XOR
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pool<SigBit> xor_fanout_once;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\ANDTERM")
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continue;
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for (auto &conn : cell->connections())
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{
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if (cell->input(conn.first))
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{
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for (auto wire_in : sigmap(conn.second))
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{
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auto xor_cell = xor_out_to_xor_cell[wire_in];
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if (xor_cell)
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{
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if (xor_fanout_once[wire_in])
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{
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log("Additional fanout found for %s into %s (type %s), duplicating\n",
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xor_cell->name.c_str(),
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cell->name.c_str(),
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cell->type.c_str());
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auto new_xor_cell = module->addCell(NEW_ID, xor_cell);
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auto new_wire = module->addWire(NEW_ID);
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new_xor_cell->setPort("\\OUT", new_wire);
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cell->setPort(conn.first, new_wire);
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}
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xor_fanout_once.insert(wire_in);
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}
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}
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}
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}
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}
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// Do the same fanout fixing for OR terms. By doing this
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// after doing XORs, both pieces will be duplicated when necessary.
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// Find all the OR outputs
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dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\ORTERM")
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{
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auto output = sigmap(cell->getPort("\\OUT")[0]);
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or_out_to_or_cell[output] = cell;
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}
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}
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// Find all of the sinks for each output from an OR
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pool<SigBit> or_fanout_once;
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for (auto cell : module->selected_cells())
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{
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for (auto &conn : cell->connections())
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{
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if (cell->input(conn.first))
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{
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for (auto wire_in : sigmap(conn.second))
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{
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auto or_cell = or_out_to_or_cell[wire_in];
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if (or_cell)
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{
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if (or_fanout_once[wire_in])
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{
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log("Additional fanout found for %s into %s (type %s), duplicating\n",
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or_cell->name.c_str(),
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cell->name.c_str(),
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cell->type.c_str());
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auto new_or_cell = module->addCell(NEW_ID, or_cell);
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auto new_wire = module->addWire(NEW_ID);
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new_or_cell->setPort("\\OUT", new_wire);
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cell->setPort(conn.first, new_wire);
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}
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or_fanout_once.insert(wire_in);
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}
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}
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}
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}
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}
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}
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}
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} Coolrunner2FixupPass;
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