coolrunner2: Fix invalid multiple fanouts of XOR/OR gates

In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:

module top(input a, input b, input clk_, output reg o, output o2);

wire clk;

BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

always @(posedge clk)
    o = a ^ b;
assign o2 = a ^ b;

endmodule
This commit is contained in:
R. Ou 2020-03-02 01:06:03 -08:00
parent a618004897
commit b9c98e0100
1 changed files with 96 additions and 0 deletions

View File

@ -386,6 +386,102 @@ struct Coolrunner2FixupPass : public Pass {
}
}
}
// Now we have to fix up some cases where shared logic can
// cause XORs to have multiple fanouts to something other than
// pterms (which is not ok)
// Find all the XOR outputs
dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\MACROCELL_XOR")
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
xor_out_to_xor_cell[output] = cell;
}
}
// Find all of the sinks for each output from an XOR
pool<SigBit> xor_fanout_once;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ANDTERM")
continue;
for (auto &conn : cell->connections())
{
if (cell->input(conn.first))
{
for (auto wire_in : sigmap(conn.second))
{
auto xor_cell = xor_out_to_xor_cell[wire_in];
if (xor_cell)
{
if (xor_fanout_once[wire_in])
{
log("Additional fanout found for %s into %s (type %s), duplicating\n",
xor_cell->name.c_str(),
cell->name.c_str(),
cell->type.c_str());
auto new_xor_cell = module->addCell(NEW_ID, xor_cell);
auto new_wire = module->addWire(NEW_ID);
new_xor_cell->setPort("\\OUT", new_wire);
cell->setPort(conn.first, new_wire);
}
xor_fanout_once.insert(wire_in);
}
}
}
}
}
// Do the same fanout fixing for OR terms. By doing this
// after doing XORs, both pieces will be duplicated when necessary.
// Find all the OR outputs
dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ORTERM")
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
or_out_to_or_cell[output] = cell;
}
}
// Find all of the sinks for each output from an OR
pool<SigBit> or_fanout_once;
for (auto cell : module->selected_cells())
{
for (auto &conn : cell->connections())
{
if (cell->input(conn.first))
{
for (auto wire_in : sigmap(conn.second))
{
auto or_cell = or_out_to_or_cell[wire_in];
if (or_cell)
{
if (or_fanout_once[wire_in])
{
log("Additional fanout found for %s into %s (type %s), duplicating\n",
or_cell->name.c_str(),
cell->name.c_str(),
cell->type.c_str());
auto new_or_cell = module->addCell(NEW_ID, or_cell);
auto new_wire = module->addWire(NEW_ID);
new_or_cell->setPort("\\OUT", new_wire);
cell->setPort(conn.first, new_wire);
}
or_fanout_once.insert(wire_in);
}
}
}
}
}
}
}
} Coolrunner2FixupPass;