mirror of https://github.com/YosysHQ/yosys.git
ice40: fix specify for inverted clocks
This commit is contained in:
Eddie Hung
parent
aac309626b
commit
3728ef1765
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@ -1507,11 +1507,11 @@ module SB_RAM40_4KNR (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
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$setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
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$setup(RADDR, negedge RCLK &&& RE && RCLKE, 203);
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$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
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$setup(RCLKE, negedge RCLK, 267);
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$setup(RCLKE, posedge RCLKN, 267);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
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$setup(RE, negedge RCLK, 98);
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$setup(RE, posedge RCLKN, 98);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
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$setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
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@ -1521,7 +1521,7 @@ module SB_RAM40_4KNR (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
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$setup(WE, posedge WCLK, 133);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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(negedge RCLK => (RDATA : 16'bx)) = 2146;
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(posedge RCLKN => (RDATA : 16'bx)) = 2146;
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endspecify
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`endif
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`ifdef ICE40_LP
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@ -1529,11 +1529,11 @@ module SB_RAM40_4KNR (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
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$setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
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$setup(RADDR, negedge RCLK &&& RE && RCLKE, 300);
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$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
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$setup(RCLKE, negedge RCLK, 393);
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$setup(RCLKE, posedge RCLKN, 393);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
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$setup(RE, negedge RCLK, 145);
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$setup(RE, posedge RCLKN, 145);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
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$setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
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@ -1543,7 +1543,7 @@ module SB_RAM40_4KNR (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
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$setup(WE, posedge WCLK, 196);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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(negedge RCLK => (RDATA : 16'bx)) = 3163;
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(posedge RCLKN => (RDATA : 16'bx)) = 3163;
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endspecify
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`endif
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`ifdef ICE40_U
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@ -1551,11 +1551,11 @@ module SB_RAM40_4KNR (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
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$setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
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$setup(RADDR, negedge RCLK &&& RE && RCLKE, 384);
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$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
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$setup(RCLKE, negedge RCLK, 503);
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$setup(RCLKE, posedge RCLKN, 503);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
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$setup(RE, negedge RCLK, 185);
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$setup(RE, posedge RCLKN, 185);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
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$setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
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@ -1565,7 +1565,7 @@ module SB_RAM40_4KNR (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
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$setup(WE, posedge WCLK, 252);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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(negedge RCLK => (RDATA : 16'bx)) = 1179;
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(posedge RCLKN => (RDATA : 16'bx)) = 1179;
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endspecify
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`endif
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endmodule
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@ -1636,7 +1636,7 @@ module SB_RAM40_4KNW (
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`ifdef ICE40_HX
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specify
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
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$setup(MASK, negedge WCLK &&& WE && WCLKE, 274);
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$setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
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$setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
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@ -1644,13 +1644,13 @@ module SB_RAM40_4KNW (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
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$setup(RE, posedge RCLK, 98);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
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$setup(WADDR, negedge WCLK &&& WE && WCLKE, 224);
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$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
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$setup(WCLKE, negedge WCLK, 267);
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$setup(WCLKE, posedge WCLKN, 267);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
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$setup(WDATA, negedge WCLK &&& WE && WCLKE, 161);
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$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
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$setup(WE, negedge WCLK, 133);
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$setup(WE, posedge WCLKN, 133);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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(posedge RCLK => (RDATA : 16'bx)) = 2146;
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endspecify
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@ -1658,7 +1658,7 @@ module SB_RAM40_4KNW (
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`ifdef ICE40_LP
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specify
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
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$setup(MASK, negedge WCLK &&& WE && WCLKE, 403);
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$setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
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$setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
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@ -1666,13 +1666,13 @@ module SB_RAM40_4KNW (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
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$setup(RE, posedge RCLK, 145);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
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$setup(WADDR, negedge WCLK &&& WE && WCLKE, 331);
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$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
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$setup(WCLKE, negedge WCLK, 393);
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$setup(WCLKE, posedge WCLKN, 393);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
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$setup(WDATA, negedge WCLK &&& WE && WCLKE, 238);
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$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
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$setup(WE, negedge WCLK, 196);
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$setup(WE, posedge WCLKN, 196);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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(posedge RCLK => (RDATA : 16'bx)) = 3163;
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endspecify
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@ -1680,7 +1680,7 @@ module SB_RAM40_4KNW (
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`ifdef ICE40_U
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specify
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
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$setup(MASK, negedge WCLK &&& WE && WCLKE, 517);
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$setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
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$setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
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@ -1688,13 +1688,13 @@ module SB_RAM40_4KNW (
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
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$setup(RE, posedge RCLK, 185);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
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$setup(WADDR, negedge WCLK &&& WE && WCLKE, 424);
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$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
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$setup(WCLKE, negedge WCLK, 503);
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$setup(WCLKE, posedge WCLKN, 503);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
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$setup(WDATA, negedge WCLK &&& WE && WCLKE, 305);
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$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
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$setup(WE, negedge WCLK, 252);
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$setup(WE, posedge WCLKN, 252);
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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(posedge RCLK => (RDATA : 16'bx)) = 1179;
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endspecify
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