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2076 Commits

Author SHA1 Message Date
Eddie Hung b4663a987b Fix attributes on $__ABC9_ASYNC[01] whitebox 2019-12-31 11:14:11 -08:00
Eddie Hung 789211d9b3 Fix incorrect $__ABC9_ASYNC[01] box 2019-12-31 11:13:50 -08:00
Niklas Nisbeth 379dcda139 ice40: Demote conflicting FF init values to a warning 2019-12-31 02:38:10 +01:00
Eddie Hung 7649ec72c9 Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor 2019-12-30 16:20:58 -08:00
Eddie Hung 543bd2de6c Update timings for Xilinx S7 cells 2019-12-30 14:36:07 -08:00
Eddie Hung eb4e767053 Do not offset FD* box timings due to -46ps Tsu 2019-12-30 14:35:10 -08:00
Eddie Hung 405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Eddie Hung a038294a87 Tidy up abc9_map.v 2019-12-30 14:19:29 -08:00
Eddie Hung d7ada66497 Add "synth_xilinx -dff" option, cleanup abc9 2019-12-30 14:13:16 -08:00
Eddie Hung 79448f9be0 Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
Eddie Hung c9e3b26412 Disable synth_gowin -abc9 as it offers no advantages yet 2019-12-30 13:28:29 -08:00
Eddie Hung aa6d06c1b5 Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" 
This reverts commit 6008bb7002.
 2019-12-30 13:28:29 -08:00
Miodrag Milanović c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Miodrag Milanovic 8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Eddie Hung 71906fab51 Nitpick cleanup for ecp5 2019-12-27 16:57:08 -08:00
Eddie Hung b7afafde22 Consistency 2019-12-27 14:52:26 -08:00
Eddie Hung 4eaa45091c Update some abc9_arrival times, add abc9_required times 2019-12-27 14:47:50 -08:00
Marcin Kościelnicki 13a3041030
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen 
xilinx_dsp: Initial DSP48A/DSP48A1 support.
 2019-12-25 16:18:44 +01:00
Marcin Kościelnicki dadaf7ed78 xilinx: Test our DSP48A/DSP48A1 simulation models. 2019-12-23 20:36:43 +01:00
Marcin Kościelnicki 666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Miodrag Milanovic 436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic 1937091f62 iopad no op for compatibility with old scripts 2019-12-21 13:21:45 +01:00
Miodrag Milanovic 2fcf683af4 Make iopad option default for all xilinx flows 2019-12-21 11:56:41 +01:00
Eddie Hung d3fc94405f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 14:07:23 -08:00
Eddie Hung 5986a4df40 Add abc9_arrival times for RAM{32,64}M 2019-12-20 14:06:59 -08:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 7928eb113c Add RAM{32,64}M to abc9_map.v 2019-12-20 13:41:23 -08:00
Eddie Hung 10e82e103f
Revert "Optimise write_xaiger" 2019-12-20 12:05:45 -08:00
Eddie Hung 45f0f1486b Add RAM{32,64}M to abc9_map.v 2019-12-19 11:24:39 -08:00
Eddie Hung 979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup 
Optimise write_xaiger
 2019-12-19 12:24:03 -05:00
Marcin Kościelnicki 8b2c9f4518 xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
Marcin Kościelnicki 561ae1c5c4 xilinx_dffopt: Keep order of LUT inputs. 
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
 2019-12-19 18:01:43 +01:00
David Shah 520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld 
ecp5: Add support for mapping PRLD FFs
 2019-12-18 19:42:17 +00:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung 5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung d910bec8e0 Update xc7/xcu bram rules 2019-12-16 13:00:58 -08:00
Eddie Hung 5d00996426 Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00
Eddie Hung 7545ab3814 Populate DID/DOD even if unused 2019-12-16 11:57:04 -08:00
Eddie Hung c4d37813cb Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q 2019-12-16 10:41:13 -08:00
Diego H f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Eddie Hung 52875b0d61
Merge pull request #1533 from dh73/bram_xilinx 
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
 2019-12-13 12:01:03 -08:00
Eddie Hung c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches 2019-12-13 08:59:17 -08:00
Eddie Hung d6514fc2e1 RAM64M8 to also have [5:0] for address 2019-12-13 08:54:19 -08:00
Eddie Hung dd7d2d8db6 Duplicate tribuf call, credit to @mwkmwkmwk 2019-12-13 08:51:05 -08:00
Eddie Hung 8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung 50e0c83560 Fix RAM64M model to have 6 bit address bus 2019-12-12 18:52:03 -08:00
Eddie Hung 7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Diego H 751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung 9ab1feeaf1 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:52 -08:00
Eddie Hung 3eed8835b5 abc9_map.v: fix Xilinx LUTRAM 2019-12-12 14:56:15 -08:00
Eddie Hung 3bd623bb05 synth_xilinx: error out if tristate without '-iopad' 2019-12-12 14:33:33 -08:00
Diego H 937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H ab6ac8327f Merge https://github.com/YosysHQ/yosys into bram_xilinx 2019-12-12 13:40:05 -06:00
Eddie Hung f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
David Shah 613334d9dc
Merge pull request #1564 from ZirconiumX/intel_housekeeping 
Intel housekeeping
 2019-12-11 08:46:10 +00:00
Dan Ravensloft 85a14895ca synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
Dan Ravensloft eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Eddie Hung 7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung 49c2e59b2a Fix comment 2019-12-09 15:44:19 -08:00
Eddie Hung fb203d2a2c ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
Eddie Hung 500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
David Shah 184c0e796a ecp5: Add support for mapping PRLD FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 13:04:36 +00:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung 98c9ea605b techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger 2019-12-06 17:05:02 -08:00
Eddie Hung c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung 02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Eddie Hung 864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Eddie Hung 0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung 19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung 258a34e6f1 Oh deary me 2019-12-04 20:33:24 -08:00
Eddie Hung b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung 31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
Marcin Kościelnicki fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Marcin Kościelnicki 10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Eddie Hung a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung f98aa1c13f Revert "Add INIT value to abc9_control" 
This reverts commit 19bfb41958.
 2019-12-03 15:40:44 -08:00
Eddie Hung ed3f359175 $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve 
name and attr
 2019-12-03 14:49:10 -08:00
Eddie Hung 1ea9ce0ad7 ice40_opt to ignore (* keep *) -ed cells 2019-12-03 14:48:39 -08:00
Eddie Hung 0add5965c7 techmap abc_unmap.v before xilinx_srl -fixed 2019-12-03 14:27:45 -08:00
Clifford Wolf 2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
Eddie Hung 19bfb41958 Add INIT value to abc9_control 2019-12-02 14:17:06 -08:00
Marcin Kościelnicki 2badaa9adb xilinx: Add missing blackbox cell for BUFPLL. 2019-11-29 16:56:27 +01:00
Eddie Hung b1ab7c16c4 clkpart -unpart into 'finalize' 2019-11-28 12:59:43 -08:00
Diego H 3a5a65829c Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-27 12:05:04 -06:00
Eddie Hung df8dc6d1fb ean call after abc{,9} 2019-11-27 09:10:34 -08:00
Eddie Hung f6c0ec1d09 Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff 2019-11-27 01:03:33 -08:00
Eddie Hung 739f530906 Move 'clean' from map_luts to finalize 2019-11-26 14:51:39 -08:00
Marcin Kościelnicki 0466c48533 xilinx: Add simulation models for IOBUF and OBUFT. 2019-11-26 08:15:20 +01:00
Eddie Hung d087024caf Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-25 12:42:09 -08:00
Eddie Hung 6a2eb5d8f9 Special abc9_clock wire to contain only clock signal 2019-11-25 12:36:13 -08:00
Marcin Kościelnicki 6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki 7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos 72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos 6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Eddie Hung eb11c06a69 For abc9, run clkpart before ff_map and after abc9 2019-11-23 10:18:22 -08:00
Martin Pietryka 97b22413e5 coolrunner2: remove spurious log_pop() call, fixes #1463 
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
 2019-11-23 06:21:40 +01:00
Eddie Hung bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Marcin Kościelnicki 1d098b7195 gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Eddie Hung 5a30e3ac3b Merge branch 'eddie/xaig_dff_adff' into xaig_dff 2019-11-21 16:15:25 -08:00
Eddie Hung af3055fe83 Add blackbox model for $__ABC9_FF_ so that clock partitioning works 2019-11-20 14:30:56 -08:00
Eddie Hung df63d75ff3 Fix INIT values 2019-11-20 11:26:59 -08:00
Eddie Hung 344619079d Do not drop async control signals in abc_map.v 2019-11-19 16:57:07 -08:00
Eddie Hung 09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Clifford Wolf 7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Pepijn de Vos 8ab412eb16 Remove dff init altogether 
The hardware does not actually support it.
In reality it is always initialised to its reset value.
 2019-11-19 15:53:44 +01:00
Marcin Kościelnicki 7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. 
This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
 2019-11-19 01:00:58 +01:00
Pepijn de Vos dd8c7e1ddd add help for nowidelut and abc9 options 2019-11-18 14:26:09 +01:00
Pepijn de Vos 32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
David Shah 51e4e29bb1 ecp5: Use new autoname pass for better cell/net names 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-15 21:03:11 +00:00
Clifford Wolf e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf 056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim 
ice40: Support for post-place-and-route timing simulations
 2019-11-14 12:07:25 +01:00
Clifford Wolf 07c854b7af Add "autoname" pass and use it in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-13 13:41:16 +01:00
Pepijn de Vos ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Pepijn de Vos ec3faa7b96 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-11 17:08:40 +01:00
Clifford Wolf 362f4f996d Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-11 15:07:29 +01:00
Pepijn de Vos 0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Marcin Kościelnicki c4bd318e76 synth_xilinx: Merge blackbox primitive libraries. 
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.

Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included.  Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.

Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).

Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
 2019-11-06 15:11:27 +01:00
Pepijn de Vos 0f6269b04c add IOBUF 2019-10-28 15:33:05 +01:00
Pepijn de Vos 903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos 2f5e9e9885 More formatting 2019-10-28 13:10:12 +01:00
Pepijn de Vos c1921b4561 really really fix formatting maybe 2019-10-28 13:01:20 +01:00
Pepijn de Vos 293b2c2de5 undo formatting fuckup 2019-10-28 12:57:12 +01:00
Pepijn de Vos f88335a8a5 add wide luts 2019-10-28 12:49:08 +01:00
Pepijn de Vos 5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Pepijn de Vos 8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
David Shah e135ed5d80 ice40: Add post-pnr ICESTORM_RAM model and fix FFs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 18:44:34 +01:00
David Shah 37dd3ad3fe ice40: Support for post-pnr timing simulation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 12:03:31 +01:00
David Shah 3506eaf290 xilinx: Add URAM288 mapping for xcup 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:44 +01:00
David Shah 6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00
Marcin Kościelnicki 7b350cacd4 xilinx: Support multiplier mapping for all families. 
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
 2019-10-22 18:06:57 +02:00
Clifford Wolf a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg 
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
 2019-10-22 17:36:54 +02:00
Pepijn de Vos 03457ee13e add a few more missing dff 2019-10-21 16:08:13 +02:00
Pepijn de Vos 8a2699c40c add negedge DFF 2019-10-21 12:31:11 +02:00
Pepijn de Vos af7bdd598e use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
Pepijn de Vos 69fb3b8db2 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-10-21 10:51:34 +02:00
David Shah fa989e59e5 ecp5: Pass -nomfs to abc9 
Fixes #1459

Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:30:41 +01:00
Sean Cross 82f60ba938 Makefile: don't assume python is called `python3` 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Miodrag Milanović b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00
N. Engelhardt 3b405d985e Call memory_dff before DSP mapping to reserve registers (fixes #1447) 2019-10-17 21:33:54 +02:00
Pepijn de Vos 72323e11a4 remove duplicate DFFR 2019-10-16 11:24:56 +02:00
David Shah e1d4e683b4 ecp5: Add ECLKBRIDGECS blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:50:33 +01:00
David Shah 7b1a6706d8 ecp5: Add attrmvcp to copy syn_useioff to driving FF 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-10 15:58:31 +01:00
David Shah 3b44e80d4b ecp5: Set syn_useioff on IO FFs to enable packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-10 15:55:16 +01:00
Marcin Kościelnicki 526fe4cb89 xilinx: Add simulation model for IBUFG. 2019-10-10 13:16:03 +02:00
Eddie Hung 304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
Eddie Hung 9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 
Rename abc_* names/attributes to more precisely be abc9_*
 2019-10-08 10:53:38 -07:00
Eddie Hung 4f0818275f Cleanup 2019-10-07 15:58:55 -07:00
Eddie Hung b2e34f932a Rename $currQ to $abc9_currQ 2019-10-07 15:31:43 -07:00
Eddie Hung bae3d8705d Update comments in abc9_map.v 2019-10-07 12:54:45 -07:00
Eddie Hung 1dc22607c3 Remove -D_ABC9 2019-10-07 12:21:52 -07:00
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung 6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung b47bb5c810 Fix typo in check_label() 2019-10-04 21:43:50 -07:00
Eddie Hung a2ef93f03a abc -> abc9 2019-10-04 17:56:38 -07:00
Eddie Hung a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung d4212d128b Use read_args for read_verilog 2019-10-04 17:27:05 -07:00
Eddie Hung 9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung 4e11782cde Oops 2019-10-04 10:36:02 -07:00
Eddie Hung c0f54d3fd5 Ohmilord this wasn't added all this time!?! 2019-10-04 10:34:16 -07:00
Miodrag Milanovic 44c3472b9f FF should be initialized to 0 2019-10-04 13:27:10 +02:00
Miodrag Milanovic 77d557d00b Add missing latch mapping 2019-10-04 12:58:11 +02:00
Eddie Hung 549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Eddie Hung 655f1b2ac5 English 2019-10-03 10:11:25 -07:00
Eddie Hung 5299884f04 More fixes 2019-10-01 13:41:08 -07:00
Eddie Hung 03ebe43e3e Escape Verilog identifiers for legality outside of Yosys 2019-10-01 13:05:56 -07:00
David Shah b424d374db ecp5: Fix shuffle_enable port 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 14:14:46 +01:00
David Shah 7a1538cd36 ecp5: Add support for mapping 36-bit wide PDP BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 13:46:36 +01:00
Eddie Hung e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung 5e9ae90cbb Add explanation to abc_map.v 2019-09-30 15:39:24 -07:00
Eddie Hung 8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung 5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung f6203e6bd6 Missing endmodule 2019-09-29 21:55:53 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 18ebb86edb FDCE_1 does not have IS_CLR_INVERTED 2019-09-29 11:25:34 -07:00
Eddie Hung f3e150d9a5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 09:21:51 -07:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung c372e7baf9 Fix box name 2019-09-27 18:49:45 -07:00
Eddie Hung 8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung b3d8a60cbd Re-order 2019-09-27 14:32:07 -07:00
Eddie Hung 90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung 143f82def2 Missing an '&' 2019-09-26 11:13:08 -07:00
Eddie Hung 84825f9378 Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once 2019-09-26 10:45:14 -07:00
Eddie Hung 033aefc0f4 Typo 2019-09-26 10:34:14 -07:00
Eddie Hung 781dda6175 select once 2019-09-26 10:15:05 -07:00
Eddie Hung 27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung 35aaa8d73a mul2dsp.v slice names 2019-09-25 22:58:55 -07:00
Eddie Hung 34aa3532fb Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit 2019-09-25 17:26:47 -07:00
Eddie Hung a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" 
This reverts commit 234738b103.
 2019-09-25 17:25:44 -07:00
Eddie Hung f4387e817c Revert "No need for $__mul anymore?" 
This reverts commit 1d875ac76a.
 2019-09-25 17:24:11 -07:00
Eddie Hung 63940913d2 Only wreduce on t:$add 2019-09-25 17:22:04 -07:00
Eddie Hung 234738b103 Remove _TECHMAP_CELLTYPE_ check since all $mul 2019-09-25 16:51:31 -07:00
Eddie Hung 1d875ac76a No need for $__mul anymore? 2019-09-25 14:06:21 -07:00
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 93363c94a2 Oops. Actually use __NAME__ in ABC_DSP48E1 macro 2019-09-25 10:33:16 -07:00
Eddie Hung b41d2fb4e4 Add (* techmap_autopurge *) to abc_unmap.v too 2019-09-23 22:02:22 -07:00
Eddie Hung 11ac37733d Add techmap_autopurge to outputs in abc_map.v too 2019-09-23 21:56:28 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 0f53893104 Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" 
This reverts commit 67c2db3486.
 2019-09-23 19:52:55 -07:00
Eddie Hung 29db96fa1f Revert "Vivado does not like zero width port connections" 
This reverts commit 895e2befa7.
 2019-09-23 19:52:54 -07:00
Eddie Hung 895e2befa7 Vivado does not like zero width port connections 2019-09-23 19:04:07 -07:00
Eddie Hung 67c2db3486 Remove (* techmap_autopurge *) from abc_unmap.v since no effect 2019-09-23 18:56:18 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung 4401e5f142 Grammar 2019-09-20 14:24:31 -07:00
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung 289cf688b7 Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 2019-09-20 09:02:29 -07:00
Eddie Hung 829e4f5d2c Revert "Move mul2dsp before wreduce" 
This reverts commit e4f4f6a9d5.
 2019-09-20 08:56:16 -07:00
Eddie Hung e4f4f6a9d5 Move mul2dsp before wreduce 2019-09-20 08:41:40 -07:00
Eddie Hung 691686f92c Tidy up, fix undriven 2019-09-19 20:04:52 -07:00
Eddie Hung 1602516a8b $__ABC_REG to have WIDTH parameter 2019-09-19 19:37:45 -07:00
Eddie Hung e09f80479e Fix DSP48E1 timing by breaking P path if MREG or PREG 2019-09-19 18:59:28 -07:00
Eddie Hung 362a803779 Revert "Different approach to timing" 
This reverts commit 41256f48a5.
 2019-09-19 18:33:38 -07:00
Eddie Hung 41256f48a5 Different approach to timing 2019-09-19 18:33:29 -07:00
Eddie Hung 5ca25b0c59 Suppress $anyseq warnings 2019-09-19 16:27:14 -07:00
Eddie Hung 595fb611a5 Use (* techmap_autopurge *) to suppress techmap warnings 2019-09-19 15:58:01 -07:00
Eddie Hung c15a35db84 D is 25 bits not 24 bits wide 2019-09-19 15:55:49 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 95db2489bd synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 2019-09-19 14:58:06 -07:00
Eddie Hung 3b9b0fcd06 Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 2019-09-19 14:57:38 -07:00
Marcin Kościelnicki 13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Eddie Hung fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Eddie Hung 25e0f0c376 Fix copy-paste 2019-09-18 12:19:16 -07:00
Eddie Hung b77cf6ba48 Mis-spell 2019-09-18 11:12:46 -07:00
Eddie Hung e992dbf2c5 Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
Eddie Hung 3ec28ec53a
Merge pull request #1379 from mmicko/sim_models 
Added simulation models for Efinix and Anlogic
 2019-09-18 10:04:27 -07:00
Miodrag Milanovic 3e9449cb0b make note that it is for latch mode 2019-09-18 17:48:16 +02:00
Miodrag Milanovic b0ca6de472 better lut handling 2019-09-18 17:45:19 +02:00
Miodrag Milanovic 8badd4d812 better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic 2019-09-15 09:37:16 +02:00
Eddie Hung 681be20ca2 Add `undef DSP48E1_INST 2019-09-13 17:07:18 -07:00
Eddie Hung 61877e1370 Fix D -> P{,COUT} delay 2019-09-13 13:32:55 -07:00
Eddie Hung d0b202c58d Add no MULT no DPORT config 2019-09-13 12:05:14 -07:00
Eddie Hung 247a63f55d Add support for MULT and DPORT 2019-09-13 11:45:55 -07:00
Eddie Hung e235dd0785 Refine diagram 2019-09-13 09:34:40 -07:00
Eddie Hung 734034a872 Add an ASCII drawing 2019-09-12 18:13:46 -07:00
Eddie Hung c52863f147 Finish explanation 2019-09-12 18:01:49 -07:00
Eddie Hung aaeaab4ac0 Rename to techmap_guard 2019-09-12 17:45:02 -07:00
Eddie Hung 6bb8e6a726 Initial DSP48E1 box support 2019-09-12 17:11:01 -07:00
Eddie Hung 3a39073302 Set more ports explicitly 2019-09-12 17:10:43 -07:00
Eddie Hung 0ebbecf833 Missing space 2019-09-11 13:06:59 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 5c1271c51c Move "(skip if -nodsp)" message to label 2019-09-10 15:26:56 -07:00
Eddie Hung f2d030a70f Be sensitive to signedness 2019-09-10 15:14:55 -07:00
Eddie Hung 76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung c460d10e60 Remove wreduce call 2019-09-10 14:17:35 -07:00
Eddie Hung f3a55d3f06 Add comment for why opt_expr is necessary 2019-09-10 14:11:56 -07:00
Eddie Hung 8514e7c32e Revert "Remove "opt_expr -fine" call" 
This reverts commit bfda921d03.
 2019-09-10 14:09:21 -07:00
Eddie Hung d3fb308181 Rename label to map_dsp 2019-09-10 13:18:10 -07:00
Eddie Hung bfda921d03 Remove "opt_expr -fine" call 2019-09-10 13:17:47 -07:00
Eddie Hung a7e6032287 Set USE_MULT and USE_SIMD 2019-09-09 20:56:29 -07:00
Marcin Kościelnicki fda94311ee synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
Pepijn de Vos 2fb20f184a Revert "add MUX support" 
It turns out that they make everything worse and they don't PnR.

This reverts commit 3eff2271d0.
 2019-09-06 11:28:17 +02:00
Pepijn de Vos 96efa63f16 fix BRAM width and init 2019-09-06 10:55:04 +02:00
Pepijn de Vos 1b9f7f49b5 add more DFF to sim lib 2019-09-06 09:01:07 +02:00
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Pepijn de Vos 5168b6ffa4 WIP aditional DFF primitives 2019-09-05 19:12:47 +02:00
Pepijn de Vos 47374a495d support bram initialisation 2019-09-05 17:25:51 +02:00
Pepijn de Vos 7a43be5e43 use singleton ground and vcc nets, apparently this makes pnr happier 2019-09-05 16:38:47 +02:00
Pepijn de Vos 3eff2271d0 add MUX support 2019-09-05 13:36:41 +02:00
Eddie Hung aa1491add3 Resolve TODO with pin assignments for SRL* 2019-09-04 15:47:36 -07:00
Eddie Hung 3732d421c5 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-04 12:37:42 -07:00
Pepijn de Vos ae93c034ad set undriven pads to zero 2019-09-04 16:29:40 +02:00
Pepijn de Vos a6d81a8d14 Merge remote-tracking branch 'diego/gowin' 2019-09-04 11:20:05 +02:00
Pepijn de Vos ec56438cf2 gowin: add splitnets to appease the PnR 2019-09-04 10:33:47 +02:00
Diego H 5aa8d7ceeb Updating gowin 2019-09-02 17:43:27 -05:00
Eddie Hung 3459d28349 Add comments 2019-09-02 12:22:15 -07:00
Eddie Hung 696f854801 Rename box 2019-09-02 12:15:11 -07:00
Eddie Hung 2fa3857963 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-02 12:13:44 -07:00
Miodrag Milanovic a3c16a0565 Fix TRELLIS_FF simulation model 2019-08-31 11:12:06 +02:00
David Shah 90b44113d8 ecp5_gsr: Fix typo 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-31 09:58:46 +01:00
Eddie Hung f33abd4eab Remove trailing space 2019-08-30 16:44:11 -07:00
Eddie Hung 723815b384 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-30 13:26:19 -07:00
Eddie Hung f0fef90e9d Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:30:46 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
David Shah 91b46ed816 ecp5: Add simulation equivalence check for Diamond FF implementations 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-30 13:27:36 +01:00
whitequark d9c621f9d1 ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. 2019-08-30 10:05:09 +00:00
whitequark 1e6b60d563 ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives. 2019-08-30 09:56:19 +00:00
whitequark 6fa8ce93e6 ecp5: add missing FD primitives. 2019-08-30 09:54:48 +00:00
whitequark 7e2825a2a4 ecp5: fix CEMUX on IFS/OFS primitives. 2019-08-30 09:42:33 +00:00
Eddie Hung 25b1670a84 Rename boxes too 2019-08-29 07:03:32 -07:00
Eddie Hung c4e5310823 Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
Eddie Hung e8e3830868 Comment out SB_MAC16 arrival time for now, need to handle all its modes 2019-08-28 19:09:29 -07:00
Eddie Hung 309684af16 Add arrival for SB_MAC16.O 2019-08-28 19:07:28 -07:00
Eddie Hung efa4ee5c0e Add arrival times for U 2019-08-28 19:03:29 -07:00
Eddie Hung 4bda902f1b LX -> LP 2019-08-28 19:02:54 -07:00
Eddie Hung 0f4e9f6bc5 Round not floor 2019-08-28 18:57:34 -07:00
Eddie Hung 927f1e3754 Add LP timings 2019-08-28 18:56:25 -07:00
Eddie Hung e3709e5ee6 LX -> LP 2019-08-28 18:51:14 -07:00
Eddie Hung a4f641f230 Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
Eddie Hung c0b99ed0e8 Do not overwrite LUT param 2019-08-28 18:45:09 -07:00
Eddie Hung 070f3ac561 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:29:25 -07:00
Eddie Hung d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung f5b4bc847c Adapt to $__ICE40_CARRY_WRAPPER 2019-08-28 17:25:05 -07:00
Eddie Hung e569f13870 Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" 
This reverts commit 2aedee1f0e.
 2019-08-28 17:22:44 -07:00
Eddie Hung 2421cb3fed Add arrival times for HX devices 2019-08-28 17:21:37 -07:00
Eddie Hung e4f89e01b5 Specify ice40 family to cells_sim.v using define 2019-08-28 17:21:12 -07:00
Eddie Hung 345a572449 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:19:02 -07:00
Eddie Hung 2aedee1f0e Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 
CARRY_WRAPPER in the same way since I0 and I3 could be used
 2019-08-28 17:07:36 -07:00
Eddie Hung 077e9d4ada Update box size and timings 2019-08-28 17:07:24 -07:00
Eddie Hung 129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung 1b08f861b6 Merge branch 'eddie/xilinx_srl' into xaig_arrival 2019-08-28 15:31:48 -07:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung 9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
David Shah 13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr 
ecp5: Add GSR and SGSR support
 2019-08-28 12:44:02 +01:00
Marcin Kościelnicki d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
David Shah fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung 455da57272 Fix spacing 2019-08-23 13:21:21 -07:00
Eddie Hung 85d39653ac Remove unused model 2019-08-23 13:20:29 -07:00
Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e} 2019-08-23 12:22:46 -07:00
Eddie Hung 78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung e658d472c8 Put attributes above port 2019-08-23 11:31:20 -07:00
Eddie Hung d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung 20f4d191b5 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:24:19 -07:00
Eddie Hung 509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung 0d0ad15898 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:23:31 -07:00
Eddie Hung a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 7188972645 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:54 -07:00
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Clifford Wolf 2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes 
Anlogic fixes and optimization
 2019-08-22 18:09:10 +02:00
Clifford Wolf 4c449caf9b Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:06:36 +02:00
Clifford Wolf 4d37710e82
Merge pull request #1281 from mmicko/efinix 
Initial support for Efinix Trion series FPGAs
 2019-08-22 18:06:02 +02:00
Eddie Hung 15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung 5ce0c31d0e Add init support 2019-08-21 13:05:10 -07:00
Eddie Hung c7af71ecde Use semicolon 2019-08-21 11:47:17 -07:00
Eddie Hung 5d0f6cbd54 techmap before read 2019-08-21 11:47:06 -07:00
Eddie Hung 8f69be9cc7 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-21 11:39:14 -07:00
Eddie Hung 584c680691 Add abc_arrival to SRL* 2019-08-21 11:27:42 -07:00
Eddie Hung 076af2e617 Missing newline 2019-08-20 20:37:52 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung 64d62710de Oops 2019-08-20 20:07:38 -07:00
Eddie Hung c26c556384 xilinx to use abc_map.v with -max_iter 1 2019-08-20 19:47:11 -07:00
Eddie Hung 6b1b03d9f7 ecp5: remove DPR16X4 from abc_unmap.v 2019-08-20 19:20:17 -07:00
Eddie Hung d46dc9c5b4 ecp5 to use -max_iter 1 2019-08-20 19:18:36 -07:00
Eddie Hung 55acf3120f ecp5 to use abc_map.v and _unmap.v 2019-08-20 18:59:03 -07:00
Eddie Hung 343039496b Add reference to FD* timing 2019-08-20 18:22:58 -07:00
Eddie Hung f1a206ba03 Revert "Remove sequential extension" 
This reverts commit 091bf4a18b.
 2019-08-20 18:17:14 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung bbab608691 Remove SRL* delays from cells_sim.v 2019-08-20 18:14:40 -07:00
Eddie Hung aa2d3af631 LUTMUX -> LUTMUX6 2019-08-20 18:08:07 -07:00
Eddie Hung 30a379b5b6 Cleanup techmap in map_luts 2019-08-20 17:59:31 -07:00
Eddie Hung 3b52d6e29c Move `techmap abc_map.v` into map_luts 2019-08-20 17:55:12 -07:00
Eddie Hung 54284aaa98 Remove delays from abc_map.v 2019-08-20 17:52:27 -07:00
Eddie Hung 96f00e9147 Typo 2019-08-20 17:51:50 -07:00
Eddie Hung 8f666ebac1 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 17:36:14 -07:00
Eddie Hung e273ed5275 Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
Eddie Hung 808f07630f Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
Eddie Hung 0079e9b4a6 Add LUTRAM delays 2019-08-20 13:53:38 -07:00
Eddie Hung 8d0cffaf20 Remove mapping rules 2019-08-20 13:11:39 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung 5eda5fc7eb Remove -icells 2019-08-20 12:41:11 -07:00
Eddie Hung be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Eddie Hung 14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
Eddie Hung 526e081342 Add arrival times for SRL outputs 2019-08-19 15:15:43 -07:00
Eddie Hung b71212ddea Add BRAM arrival times 2019-08-19 12:46:35 -07:00
Eddie Hung 2f86366087 Add reference to source of Tclktoq timing 2019-08-19 12:39:22 -07:00
Eddie Hung d02ef8c73f Add 'abc_arrival' attribute for flop outputs 2019-08-19 11:32:18 -07:00
Eddie Hung f25837f8e8 Update box timings 2019-08-19 11:31:40 -07:00
Eddie Hung ba2261e21a Move from cell attr to module attr 2019-08-19 11:18:33 -07:00
Eddie Hung 2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00
Eddie Hung d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung e301440a0b Use attributes instead of params 2019-08-19 09:51:49 -07:00
Miodrag Milanovic 4a32e29445 Merge remote-tracking branch 'upstream/master' into anlogic_fixes 2019-08-18 11:47:46 +02:00
whitequark 101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Eddie Hung 24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung 1c57b1e7ea Update abc_* attr in ecp5 and ice40 2019-08-16 15:56:57 -07:00
Eddie Hung 562c9e3624 Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules 2019-08-16 15:40:53 -07:00
Eddie Hung 41191f1ea4
Merge pull request #1250 from bwidawsk/master 
techlibs/intel: Clean up Makefile
 2019-08-16 14:07:09 -07:00
Eddie Hung 261daffd9d Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-15 12:19:47 -07:00
Eddie Hung e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Marcin Kościelnicki 3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki 49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung 2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
David Shah edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung 8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Miodrag Milanovic 5f561bdcb1 Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
Miodrag Milanovic 2897fe4d09 Fix formating 2019-08-11 17:05:24 +02:00
Miodrag Milanovic ead2b52b5a one bit enable signal 2019-08-11 13:59:39 +02:00
Miodrag Milanovic aa0c37722a fix mixing signals on FF mapping 2019-08-11 11:40:15 +02:00
Miodrag Milanovic 853c755a0c Replaced custom step with setundef 2019-08-11 11:01:46 +02:00
Miodrag Milanovic e609537e38 Fixed data width 2019-08-11 10:46:48 +02:00
Miodrag Milanovic 8c8100e0df Adding new pass to fix carry chain 2019-08-11 10:17:49 +02:00
Miodrag Milanovic b3a91d6508 cleanup 2019-08-11 08:37:56 +02:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc 
Add a few comments to document $alu and $lcu
 2019-08-10 09:46:46 +02:00
Eddie Hung 6d254f2de8 Add wreduce to synth_ice40 -dsp as well 2019-08-09 17:05:56 -07:00
Eddie Hung 0b5b56c1ec Pack partial-product adder DSP48E1 packing 2019-08-09 15:19:33 -07:00
Eddie Hung 041defc5a6 Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
Eddie Hung acfb672d34 A bit more on where $lcu comes from 2019-08-09 09:50:47 -07:00
Eddie Hung 5aef998957 Add more comments 2019-08-09 09:48:17 -07:00
Miodrag Milanovic d51b135e33 Fix CO 2019-08-09 12:37:10 +02:00
Miodrag Milanovic 7a860c5623 Merge remote-tracking branch 'upstream/master' into efinix 2019-08-09 09:46:37 +02:00
Eddie Hung 1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v 2019-08-08 16:33:20 -07:00
Eddie Hung 2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung 162eab6b74 Combine techmap calls 2019-08-08 10:55:48 -07:00
Eddie Hung 7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung 57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung 13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
Eddie Hung dae7c59358 Add a few comments to document $alu and $lcu 2019-08-08 10:05:28 -07:00
David Shah 0492b8b541 ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:18:59 +01:00
David Shah cb84ed2326 ecp5: Bring up to date with mul2dsp changes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:14:09 +01:00
David Shah 83b2e02723 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-08 11:40:09 +01:00
David Shah b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah 57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung 9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung 675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung 6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung a206aed977 Run "opt_expr -fine" instead of "wreduce" due to #1213 2019-08-07 13:59:07 -07:00
Eddie Hung e3d898dccb Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-07 13:44:08 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00