mirror of https://github.com/YosysHQ/yosys.git
Update abc_* attr in ecp5 and ice40
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@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
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endmodule
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// ---------------------------------------
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(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
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module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
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output S0, S1, COUT);
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(* abc_box_id=1, lib_whitebox *)
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module CCU2C(
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(* abc_carry_in *) input CIN,
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input A0, B0, C0, D0, A1, B1, C1, D1,
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output S0, S1,
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(* abc_carry_out *) output COUT
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);
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parameter [15:0] INIT0 = 16'h0000;
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parameter [15:0] INIT1 = 16'h0000;
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parameter INJECT1_0 = "YES";
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@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
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endmodule
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// ---------------------------------------
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//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
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//(* abc_box_id=2 *)
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module TRELLIS_DPR16X4 (
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input [3:0] DI,
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input [3:0] WAD,
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input WRE, WCK,
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input [3:0] RAD,
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(* abc_scc_break *) input [3:0] DI,
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(* abc_scc_break *) input [3:0] WAD,
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(* abc_scc_break *) input WRE,
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input WCK,
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input [3:0] RAD,
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output [3:0] DO
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);
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parameter WCKMUX = "WCK";
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@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
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assign CO = (I0 && I1) || ((I0 || I1) && CI);
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endmodule
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(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
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module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
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(* abc_box_id = 1, lib_whitebox *)
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module \$__ICE40_FULL_ADDER (
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(* abc_carry_out *) output CO,
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output O,
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input A,
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input B,
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(* abc_carry_in *) input CI
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);
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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