Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER

2019-08-12 12:19:25 -07:00 · 2019-08-12 12:19:25 -07:00 · 8a2480526f
parent 12c692f6ed
commit 8a2480526f
1 changed files with 1 additions and 1 deletions
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
    .WIDTH(4),
    .LUT(LUT)
  ) lut (
-    .A({I3,B,A,I0}),
+    .A({I0,A,B,I3}),
    .Y(O)
  );
 endmodule