Add assign PCOUT = P to DSP48E1

2019-08-13 12:19:26 -07:00 · 2019-08-13 12:19:26 -07:00 · ed4b2834ef
parent 0597a3ea23
commit ed4b2834ef
1 changed files with 2 additions and 0 deletions
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@ -784,4 +784,6 @@ module DSP48E1 (
        end
    endgenerate

+    assign PCOUT = P;
+
 endmodule