diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 2731cb454..02ce0d61b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -784,4 +784,6 @@ module DSP48E1 (
         end
     endgenerate
 
+    assign PCOUT = P;
+
 endmodule