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Allow whitebox modules to be overwritten

This commit is contained in:
Eddie Hung 2019-08-07 16:40:24 -07:00
parent 9962e6fc1a
commit 9776084eda
2 changed files with 1 additions and 3 deletions
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2
frontends/ast/ast.cc
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@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
if (design->has((*it)->str)) {
RTLIL::Module *existing_mod = design->module((*it)->str);
if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str());
} else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s:%d.\n",

2
techlibs/ice40/tests/test_arith.ys
View File

@ -8,8 +8,6 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
delete A:whitebox # Necessary since whiteboxes cannot
# be overwritten...
synth_ice40 -top gate
read_verilog test_arith.v