mirror of https://github.com/YosysHQ/yosys.git
DSP48E1 sim model: seq test working
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
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f6605c7dc0
commit
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@ -547,7 +547,7 @@ module DSP48E1 (
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end
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// C and D registers
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if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= D; end
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if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
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else always @* Cr <= C;
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if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
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@ -608,7 +608,7 @@ module DSP48E1 (
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// X multiplexer
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case (OPMODEr[1:0])
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2'b00: X = 48'b0;
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2'b01: begin X = $signed(M);
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2'b01: begin X = $signed(Mr);
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`ifdef __ICARUS__
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if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
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`endif
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@ -631,7 +631,7 @@ module DSP48E1 (
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`endif
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end
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2'b10: Y = {48{1'b1}};
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2'b11: Y = C;
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2'b11: Y = Cr;
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default: Y = 48'bx;
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endcase
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@ -644,7 +644,7 @@ module DSP48E1 (
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
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`endif
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end
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3'b011: Z = C;
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3'b011: Z = Cr;
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3'b100: begin Z = P;
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`ifdef __ICARUS__
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
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@ -659,7 +659,7 @@ module DSP48E1 (
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// Carry in
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wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17];
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reg CARRYINr, A24_xnor_B17;
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reg CARRYINr = 1'b0, A24_xnor_B17 = 1'b0;
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generate
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if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end
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else always @* CARRYINr = CARRYIN;
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@ -698,6 +698,7 @@ module DSP48E1 (
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wire [3:0] int_carry_in, int_carry_out, ext_carry_out;
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wire [47:0] alu_sum;
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assign int_carry_in[0] = 1'b0;
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wire [3:0] carryout_reset;
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generate
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if (USE_SIMD == "FOUR12") begin
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@ -715,6 +716,7 @@ module DSP48E1 (
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maj_xyz_gated[23] ^ int_carry_out[1],
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maj_xyz_gated[11] ^ int_carry_out[0]
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};
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assign carryout_reset = 4'b0000;
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end else if (USE_SIMD == "TWO24") begin
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assign maj_xyz_simd_gated = {
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maj_xyz_gated[47:24],
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@ -728,6 +730,7 @@ module DSP48E1 (
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maj_xyz_gated[23] ^ int_carry_out[1],
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1'bx
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};
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assign carryout_reset = 4'b0x0x;
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end else begin
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assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin};
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assign int_carry_in[3:1] = int_carry_out[2:0];
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@ -735,6 +738,7 @@ module DSP48E1 (
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int_carry_out[3],
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3'bxxx
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};
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assign carryout_reset = 4'b0xxx;
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end
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genvar i;
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@ -745,6 +749,9 @@ module DSP48E1 (
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wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum;
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initial P = 48'b0;
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initial CARRYOUT = carryout_reset;
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initial CARRYCASCOUT = 1'b0;
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initial MULTSIGNOUT = 1'b0;
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wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx :
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((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out);
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wire CARRYCASCOUTd = ext_carry_out[3];
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@ -755,7 +762,7 @@ module DSP48E1 (
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always @(posedge CLK)
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if (RSTP) begin
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P <= 48'b0;
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CARRYOUT <= 4'b0;
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CARRYOUT <= carryout_reset;
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CARRYCASCOUT <= 1'b0;
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MULTSIGNOUT <= 1'b0;
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end else if (CEP) begin
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@ -4,7 +4,7 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v >
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if [ ! -f "test_dsp_model_ref.v" ]; then
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cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
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fi
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for tb in mult_noreg_nopreadd_nocasc
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for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc
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do
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iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
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vvp -N ./test_dsp_model
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@ -94,7 +94,7 @@ module testbench;
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if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
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if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
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if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000 || ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11)) config_valid = 0;
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if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0;
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if (OPMODE[6:4] == 3'b111) config_valid = 0;
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if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0;
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@ -119,14 +119,16 @@ module testbench;
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{OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0;
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = ~0;
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#5;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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#5;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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repeat (10) begin
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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end
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0;
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repeat (300) begin
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@ -358,4 +360,39 @@ module mult_noreg_nopreadd_nocasc;
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.IS_INMODE_INVERTED (5'b0),
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.IS_OPMODE_INVERTED (7'b0)
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) testbench ();
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endmodule
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module mult_allreg_nopreadd_nocasc;
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testbench #(
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.ACASCREG (1),
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.ADREG (1),
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.ALUMODEREG (1),
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.AREG (2),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (1),
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.BREG (2),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (1),
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.CARRYINSELREG (1),
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.CREG (1),
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.DREG (1),
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.INMODEREG (1),
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.MREG (1),
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.OPMODEREG (1),
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.PREG (1),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("FALSE"),
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.USE_MULT ("DYNAMIC"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("ONE48"),
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.MASK (48'h3FFFFFFFFFFF),
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.PATTERN (48'h000000000000),
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.IS_ALUMODE_INVERTED(4'b0),
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.IS_CARRYIN_INVERTED(1'b0),
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.IS_CLK_INVERTED (1'b0),
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.IS_INMODE_INVERTED (5'b0),
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.IS_OPMODE_INVERTED (7'b0)
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) testbench ();
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endmodule
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