riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,262 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

1590 Commits

Author SHA1 Message Date
Eddie Hung c492a3a1c4 write_xaiger duplicate inout port into out port with $inout.out suffix 2019-02-25 18:39:36 -08:00
Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. 
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
 2019-02-25 16:18:13 -08:00
Eddie Hung 292f80d231 Cleanup abc9 code 2019-02-25 15:20:56 -08:00
Eddie Hung 5180338e80 write_xaiger to write __dummy_o__ for -symbols too 2019-02-21 17:03:18 -08:00
Eddie Hung 085ed9f487 Add attribution 2019-02-21 14:40:13 -08:00
Eddie Hung 2f96a0ed32 write_xaiger to use original bit for co, not sigmap()-ed bit 2019-02-21 11:15:25 -08:00
Eddie Hung 01f8d50ba2 Remove swap file 2019-02-20 16:17:01 -08:00
Eddie Hung f89b112fbf write_aiger: fix CI/CO and symbols 2019-02-20 15:35:32 -08:00
Eddie Hung ef60ca1717 write_xaiger to not write latches, CO/PO fixes 2019-02-20 11:09:13 -08:00
Eddie Hung f9af902532 Merge branch 'master' into xaig 2019-02-19 14:20:04 -08:00
Eddie Hung 11480b4fa3 Instead of INIT param on cells, use initial statement with hier ref as 
per @cliffordwolf
 2019-02-17 12:18:12 -08:00
Eddie Hung 17cd5f759f Merge https://github.com/YosysHQ/yosys into dff_init 2019-02-17 11:49:06 -08:00
Eddie Hung 30f1204721 Cleanup 2019-02-16 22:22:17 -08:00
Eddie Hung 76c35f80f4 Cleanup 2019-02-16 21:09:48 -08:00
Eddie Hung 6a57de9013 write_xaiger to support non-bit cell connections, and cope with COs for -O 2019-02-16 21:00:39 -08:00
Eddie Hung b9a305b85d write_aiger -O to write dummy output as __dummy_o__ 2019-02-16 20:08:59 -08:00
Eddie Hung 0c409e6d8c Tidy up write_xaiger 2019-02-16 08:48:33 -08:00
Eddie Hung 2c1655ae94 write_aiger() to perform CI/CO post-processing and fix symbols 2019-02-16 08:46:25 -08:00
Eddie Hung 486a270415 Fixes needed for DFF circuits 2019-02-15 15:22:18 -08:00
Jim Lawson c245041bfe Removed unused variables, functions. 2019-02-15 12:00:28 -08:00
Eddie Hung 3ac5b65197 write_xaiger to cope with unknown cells by transforming them to CI/CO 2019-02-15 11:51:21 -08:00
Jim Lawson fc1c9aa11f Update cells supported for verilog to FIRRTL conversion. 
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
 2019-02-15 11:14:17 -08:00
Eddie Hung c69fba8de5 More cleanup 2019-02-14 14:52:47 -08:00
Eddie Hung 7328775584 More cleanup of write_xaiger 2019-02-14 14:48:38 -08:00
Eddie Hung afa4389445 Get rid of formal stuff from xaiger backend 2019-02-14 13:27:26 -08:00
Eddie Hung f0f5d8a5cc Merge remote-tracking branch 'origin/read_aiger' into xaig 2019-02-13 14:09:36 -08:00
Eddie Hung 06cf0555ee Merge https://github.com/YosysHQ/yosys into xaig 2019-02-13 14:08:31 -08:00
Clifford Wolf 1f2548a564
Merge pull request #802 from whitequark/write_verilog_async_mem_ports 
write_verilog: correctly emit asynchronous transparent ports
 2019-02-12 14:41:34 +01:00
Eddie Hung ecd2446132 Add write_xaiger 2019-02-11 15:18:42 -08:00
Eddie Hung db08afe146 Copy backends/aiger/aiger.cc to xaiger.cc 2019-02-08 14:53:12 -08:00
Eddie Hung 20ca795b87 Remove check for cell->name[0] == '$' 2019-02-06 14:53:40 -08:00
Eddie Hung c373640a3a Refactor 2019-02-06 14:28:44 -08:00
Eddie Hung 8241db6960 write_verilog to cope with init attr on q when -noexpr 2019-02-06 14:17:09 -08:00
Clifford Wolf e112d2fbf5 Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-06 16:35:59 +01:00
whitequark da65e1e8d9 write_verilog: correctly emit asynchronous transparent ports. 
This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.
 2019-01-29 02:24:00 +00:00
Clifford Wolf 81581f24fc
Merge pull request #800 from whitequark/write_verilog_tribuf 
write_verilog: write $tribuf cell as ternary
 2019-01-27 09:23:41 +01:00
whitequark 3d7925ad9f write_verilog: write $tribuf cell as ternary. 2019-01-27 00:24:06 +00:00
whitequark 42c47a83da write_verilog: escape names that match SystemVerilog keywords. 2019-01-27 00:03:53 +00:00
Clifford Wolf 54dc33b905 Add "write_edif -gndvccy" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 13:33:11 +01:00
Clifford Wolf 6c5049f016 Fix handling of $shiftx in Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 10:55:27 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Larry Doolittle 99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Clifford Wolf 23bb77867f Minor style fixes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 20:02:39 +01:00
makaimann abf5930a33 Add btor ops for $mul, $div, $mod and $concat 2018-12-17 10:45:17 -08:00
whitequark ca866d384e write_verilog: handle the $shift cell. 
The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule
 2018-12-16 18:46:32 +00:00
Clifford Wolf ddff75b60a
Merge pull request #736 from whitequark/select_assert_list 
select: print selection if a -assert-* flag causes an error
 2018-12-16 16:45:49 +01:00
whitequark fccaa25ec1 write_verilog: add a missing newline. 2018-12-16 15:22:34 +00:00
Clifford Wolf f481ad4d44
Merge pull request #729 from whitequark/write_verilog_initial 
write_verilog: correctly map RTLIL `sync init`
 2018-12-16 15:50:16 +01:00
Clifford Wolf 0b9bb852c6 Add yosys-smtbmc support for btor witness 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-10 03:43:07 +01:00
Clifford Wolf 47a5dfdaa4 Add "yosys-smtbmc --btorwit" skeleton 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-08 06:59:27 +01:00
Clifford Wolf ed3c57fad3 Fix btor init value handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-08 06:21:31 +01:00
whitequark 7fe770a441 write_verilog: correctly map RTLIL `sync init`. 2018-12-07 18:55:08 +00:00
Clifford Wolf 82aaf6d908 Add "write_aiger -I -O -B" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-12 09:27:33 +01:00
Clifford Wolf 825b4c1aa9
Merge pull request #693 from YosysHQ/rlimit 
improve rlimit handling in smtio.py
 2018-11-07 20:16:40 +01:00
Clifford Wolf b54bf7c0f9 Limit stack size to 16 MB on Darwin 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-07 15:32:34 +01:00
Clifford Wolf f6c4485a3a Run solver in non-incremental mode whem smtio.py is configured for non-incremental solving 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 11:11:05 +01:00
Clifford Wolf 4c50e3abb9 Fix for improved smtio.py rlimit code 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 10:09:03 +01:00
Clifford Wolf 79075d123f Improve stack rlimit code in smtio.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 10:05:23 +01:00
Arjen Roodselaar 2b93542171 Use conservative stack size for SMT2 on MacOS 2018-11-04 21:58:09 -08:00
Clifford Wolf d0acea4f2e Add proper error message for when smtbmc "append" fails 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 14:41:28 +01:00
Clifford Wolf b6781c6f4b Add support for signed $shift/$shiftx in smt2 back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 11:40:58 +01:00
rafaeltp c7770d9eea adding offset info to memories 2018-10-18 16:22:33 -07:00
rafaeltp 609f46eeb7 adding offset info to memories 2018-10-18 16:20:21 -07:00
Clifford Wolf f4ad05e133
Merge pull request #663 from aman-goel/master 
Update to .smv backend
 2018-10-17 12:18:57 +02:00
Aman Goel 749b3ed62a Minor update 2018-10-15 13:54:12 -04:00
Clifford Wolf 115ca57647 Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:41:30 +02:00
Aman Goel 90e0938f9a Update to .smv backend 
Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
 2018-10-01 19:03:10 -04:00
Miodrag Milanovic 41affeeeb9 added prefix to FDirection constants, fixing windows build 2018-09-21 20:43:49 +02:00
acw1251 efac8a45a6 Fixed typo in "verilog_write" help message 2018-09-18 13:34:30 -04:00
Clifford Wolf 12440fcc8f Add $lut support to Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-06 00:18:01 +02:00
Jim Lawson 380c6f0e97 Remove unused functions. 2018-08-27 10:18:33 -07:00
Jim Lawson 93d19dc2fb Add support for module instances. 
Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
 2018-08-23 14:35:11 -07:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf dfc0c8ffc8
Merge pull request #576 from cr1901/no-resource 
Gate POSIX-only signals and resource module to only run on POSIX Pyth…
 2018-08-15 14:00:19 +02:00
Clifford Wolf 1dd156f516 Fix use of signed integers in JSON back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 23:31:25 +02:00
jpathy 7db05b2cc1
Use `realpath` 
Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.
 2018-08-06 06:51:07 +00:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
William D. Jones 0caa62802c Gate POSIX-only signals and resource module to only run on POSIX Python implementations. 2018-07-06 01:44:34 -04:00
Sergiusz Bazanski 1690dafde1 Fix protobuf build 2018-06-20 19:28:43 +01:00
Serge Bazanski 53e9a1549c Add Protobuf backend 
Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
 2018-06-19 13:34:56 +01:00
Clifford Wolf d9a2b43014 Add $dlatch support to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-22 16:03:26 +02:00
Clifford Wolf 5ca91ca019 Add "write_blif -inames -iattr" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-15 14:07:21 +02:00
Clifford Wolf 4d6af2969c Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constants 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-04 18:12:27 +02:00
Clifford Wolf 25a864fc73 Fixed -stbv handling in SMT2 back-end 2018-04-04 17:28:07 +02:00
Clifford Wolf dd5fab69c1 Add smtio status msgs when --progress is inactive 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-29 21:59:30 +02:00
Clifford Wolf a48c7e5abf Bugfix in smtio.py VCD file generator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-29 12:45:31 +02:00
Clifford Wolf 77bd645c35 Add $mem support to SMT2 clock tagging 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 02:11:20 +02:00
Clifford Wolf 3f00702475 Improve yosys-smtbmc log output and error handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-17 18:06:17 +01:00
Clifford Wolf 4d4e3a8ca6 Improve handling of invalid check-sat result in smtio.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-17 12:17:53 +01:00
Clifford Wolf 3545c0fffb Remove debug prints from yosys-smtbmc VCD writer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-08 16:24:35 +01:00
Clifford Wolf 8b604004da Check results of (check-sat) in yosys-smtbmc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-07 22:54:19 +01:00
Clifford Wolf cedbc35f4b Imporove yosys-smtbmc error handling, Improve VCD output 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-05 12:17:22 +01:00
Clifford Wolf 8b7602e660 Improve SMT2 encoding of $reduce_{and,or,bool} 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 21:22:20 +01:00
Clifford Wolf 45a6fce92c Fix a hangup in yosys-smtbmc error handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 21:13:30 +01:00
Clifford Wolf ae4e204c76 Improved error handling in yosys-smtbmc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-03 20:00:07 +01:00
Clifford Wolf a44e1edaa3 Terminate running SMT solver when smtbmc is terminated 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-03 14:50:40 +01:00
Clifford Wolf 3ced2cca6e Fix smtbmc smtc/aiw parser for wire names containing [] 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-03 14:15:49 +01:00
Clifford Wolf 90ae426078 Mangle names with square brackets in VCD files to work around issues in gtkwave 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-01 14:15:27 +01:00
Clifford Wolf 675dd5347a Small fixes and improvements in $allconst/$allseq handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 11:58:44 +01:00
Clifford Wolf b13e6bd375 Add smtbmc support for exist-forall problems 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 19:33:30 +01:00
Clifford Wolf 17583b6a21 Add support for mockup clock signals in yosys-smtbmc vcd output 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-20 17:45:22 +01:00
Clifford Wolf c9672e2e2e Fix handling of zero-length cell connections in SMT2 back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-08 19:12:12 +01:00
Clifford Wolf e4f0218907 Fixed gcc 7.2 "statement will never be executed" warning 2018-02-03 14:31:47 +01:00
Clifford Wolf e97f10b142 Fix smtio.py for large SMT2 S-expressions 2018-01-29 12:34:28 +01:00
Clifford Wolf 54aeca0983 Move user-provided smt2 info stmts to the top of the yosys-smtbmc smt2 output 2018-01-18 14:25:22 +01:00
Clifford Wolf 9804ebedbf Add "no driver for signal bit" error msg to btor back-end 2017-12-24 17:30:36 +01:00
Clifford Wolf 292984896b Simple fix BTOR memory encoding 2017-12-17 18:57:54 +01:00
Clifford Wolf bbdcc1f9d4 Improve BTOR memory encoding 2017-12-17 18:55:17 +01:00
Clifford Wolf 30f23281ed Add array support to btor back-end 2017-12-15 02:19:06 +01:00
Clifford Wolf ad901671c5 Add $anyconst/$anyseq support to btor back-end 2017-12-15 00:40:24 +01:00
Clifford Wolf 162c29bd6b Merge branch 'master' into btor-ng 2017-12-14 03:13:47 +01:00
Clifford Wolf 9419de3e37 Add yosys-smtbmc VCD writer support for memories with async writes 2017-12-14 03:06:00 +01:00
Clifford Wolf a48ec49017 Merge branch 'master' into btor-ng 2017-12-14 02:17:01 +01:00
Clifford Wolf 2625da6440 Add smt2 back-end support for async write memories 2017-12-14 02:07:10 +01:00
Clifford Wolf 546de7fa4f Add "write_btor -s" mode 2017-12-13 00:15:44 +01:00
Clifford Wolf 0881bbf2e7 Add state initval handling to btor back-end 2017-12-12 23:44:08 +01:00
Clifford Wolf f697282246 Add btor back-end support for 'x' constants 2017-12-12 21:48:55 +01:00
Clifford Wolf 82d1fd77de Add btor $shift/$shiftx support 2017-12-11 14:24:19 +01:00
Clifford Wolf cc119b5232 Fix btor back-end shift handling 2017-12-10 08:40:11 +01:00
Clifford Wolf 133a0f4978 Add support for $pmux in btor back-end 2017-12-10 08:11:08 +01:00
Clifford Wolf 83cf736309 Add support for more cell types to btor back-end 2017-12-10 07:16:47 +01:00
Clifford Wolf 63343aeaaa Fix btor concat 2017-12-09 05:58:14 +01:00
Clifford Wolf da91b31bb2 Fixed "yosys-smtbmc -g" handling of no solution 2017-11-27 19:43:36 +01:00
Clifford Wolf b981e5aa69 Fixed "yosys-smtbmc -g" handling of no solution 2017-11-27 17:42:32 +01:00
Clifford Wolf e3a51b3e87 Bugfixes in new BTOR back-end 2017-11-24 18:13:41 +01:00
Clifford Wolf 60d1129506 Progress in new BTOR back-end 2017-11-23 23:44:39 +01:00
Clifford Wolf b3d6b277ea Progress in new BTOR back-end 2017-11-23 18:50:10 +01:00
Clifford Wolf cc2495d48d Progress in new BTOR back-end 2017-11-23 18:14:53 +01:00
Clifford Wolf e41dcaa759 Progress with new BTOR backend 2017-11-23 08:28:29 +01:00
Clifford Wolf 6ee305553a Add skeleton for new BTOR back-end 2017-11-23 06:38:57 +01:00
Clifford Wolf eceacdb9a3 Remove old BTOR back-end 2017-11-23 04:28:51 +01:00
Clifford Wolf 455c1c9d97 Fix SMT2 handling of initstate in sub-modules 2017-10-29 13:21:20 +01:00
Clifford Wolf 1170508264 Improve smtio performance by using reader thread, not writer thread 2017-10-26 01:01:55 +02:00
Clifford Wolf f513494f5f Use separate writer thread for talking to SMT solver to avoid read/write deadlock 2017-10-25 19:59:56 +02:00
Clifford Wolf 76326c163a Improve p_* functions in smtio.py 2017-10-25 15:45:32 +02:00
Clifford Wolf c672c321e3 Capsulate smt-solver read/write in separate functions 2017-10-25 13:37:11 +02:00
Clifford Wolf dd46d76394 Fix a bug in yosys-smtbmc in ROM handling 2017-10-25 13:05:14 +02:00
Clifford Wolf adf1754729 Add $shiftx support to verilog front-end 2017-10-07 13:40:54 +02:00
Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73 e480847753 Fixed wrong declaration in Verilog backend 2017-10-01 11:11:32 -05:00
dh73 cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
Clifford Wolf c2d737457a Fix bug in write_smt2 (export logic driving hierarchical cells before exporting regs) 2017-08-25 11:44:48 +02:00
Clifford Wolf 48b2b376d0 Add "yosys-smtbmc --smtc-init --smtc-top --noinit" 2017-08-04 17:09:08 +02:00
Clifford Wolf 3a8f6f0f51 Add verilator support to testbenches generated by yosys-smtbmc 2017-07-21 14:33:29 +02:00
Clifford Wolf 10c7709e68 Generate FSM-style testbenches in smtbmc 2017-07-12 15:57:04 +02:00
Clifford Wolf 4a8c131fa7 Fix the fixed handling of x-bits in EDIF back-end 2017-07-11 17:45:29 +02:00
Clifford Wolf 479be3cec7 Fix handling of x-bits in EDIF back-end 2017-07-11 17:38:19 +02:00
Clifford Wolf 9557fd2a36 Add attributes and parameter support to JSON front-end 2017-07-10 13:17:38 +02:00
Clifford Wolf 3c693b6561 Change s/asserts/assertions/ in yosys-smtbmc log messages 2017-07-07 11:52:25 +02:00
Clifford Wolf 8f7404f82c Add "yosys-smtbmc --presat" 2017-07-07 02:47:30 +02:00
Clifford Wolf 5442554e6f Fix generation of multiple outputs for same AIG node in write_aiger 2017-07-05 14:23:54 +02:00
Clifford Wolf 37af6294bd Add write_table command 2017-07-05 12:13:53 +02:00
Clifford Wolf 3e0948e16f Remove unneeded delays in smtbmc vlogtb 2017-07-03 15:37:17 +02:00
Clifford Wolf 287831dca3 Include output ports with constant driver in AIGER output 2017-07-03 14:53:17 +02:00
Clifford Wolf ea805af6f5 Add "yosys-smtbmc --vlogtb-top" 2017-07-01 18:19:23 +02:00
Clifford Wolf 7d2fb6e2fc Fix smtbmc vlogtb bug in $anyseq handling 2017-07-01 02:13:32 +02:00
Clifford Wolf 8f8baccfde Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg" 2017-06-07 12:30:24 +02:00
Clifford Wolf c365e33fd7 Fix AIGER back-end for multiple symbols per input/latch/output/property 2017-05-30 19:09:11 +02:00
Clifford Wolf 9ed4c9d710 Improve write_aiger handling of unconnected nets and constants 2017-05-28 11:31:35 +02:00
Clifford Wolf d9201b85f3 Change default smt2 solver to yices (Yices 2 has switched its license to GPL) 2017-05-27 11:56:01 +02:00
Clifford Wolf 2122ae69b3 Add workaround for CBMC bug to SimpleC back-end 2017-05-17 21:07:54 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf 9f4fbc5e74 Add <modname>_init() function generator to simpleC back-end 2017-05-16 19:34:07 +02:00
Clifford Wolf 35be567605 Improve simplec back-end 2017-05-16 08:50:23 +02:00
Clifford Wolf 8d3c706459 Improve simplec back-end 2017-05-15 13:21:59 +02:00
Clifford Wolf 9c397ea78b Improve simplec back-end 2017-05-14 13:14:49 +02:00
Clifford Wolf 628daab277 Improve simplec back-end 2017-05-13 18:47:31 +02:00
Clifford Wolf ef7594ce3d Improve simplec back-end 2017-05-12 22:39:16 +02:00
Clifford Wolf 7931e1ebb4 Added support for more gate types to simplec back-end 2017-05-12 17:42:31 +02:00
Clifford Wolf bd4ed19887 Add first draft of simple C back-end 2017-05-12 14:13:33 +02:00
Clifford Wolf 1a4b7c6bfa Fix boolector support in yosys-smtbmc 2017-05-08 14:33:22 +02:00
Clifford Wolf 106e44f406 Add "write_smt2 -stdt" mode 2017-03-20 12:00:35 +01:00
Clifford Wolf 0ac72e759d Add generation of logic cells to EDIF back-end runtest.py 2017-03-19 14:57:40 +01:00
Clifford Wolf 850f8299a9 Fix EDIF: portRef member 0 is always the MSB bit 2017-03-19 14:53:28 +01:00
Clifford Wolf 1390e9a0a7 Add simple EDIF test case generator and checker 2017-03-18 15:00:03 +01:00
Clifford Wolf c855353986 Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg 2017-03-04 23:41:54 +01:00
Clifford Wolf a6ca28276e Add write_aiger $anyseq support 2017-03-02 16:39:48 +01:00
Clifford Wolf fbd52ec6dd Use hex addresses in smtbmc vcd mem traces 2017-02-28 13:54:50 +01:00
Clifford Wolf 2203562268 Add smtbmc support for memory vcd dumping 2017-02-26 21:26:32 +01:00
Clifford Wolf 80ecd7a26f Fix extra newline bug in write_smt2 2017-02-26 14:41:27 +01:00
Clifford Wolf 6e152f7aa1 Fix bug in smtio unroll code 2017-02-26 14:39:07 +01:00
Clifford Wolf 66a1617b69 Fix assert checking in "yosys-smtbmc -c --append" 2017-02-26 11:06:26 +01:00
Clifford Wolf fd1cc0c73d Improve (and fix for stbv mode) SMT2 memory API 2017-02-26 10:58:34 +01:00
Clifford Wolf 38bf458037 Add support for "yosys-smtbmc -c --append" 2017-02-25 23:41:40 +01:00
Clifford Wolf c7d1286728 Improve "write_edif" help message 2017-02-25 16:35:53 +01:00
Clifford Wolf dfddf391f9 Move EdifNames out of double-private namespace 2017-02-25 16:29:27 +01:00
Clifford Wolf 8c61ecdd6e Clean up edif code, swap bit indexing of "upto" ports 2017-02-25 16:28:34 +01:00
Clifford Wolf b76c89a5dd Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master 2017-02-25 15:59:02 +01:00
Clifford Wolf dac0842d61 Add $live and $fair support to AIGER back-end. 2017-02-25 13:07:15 +01:00
Clifford Wolf 7af9727f78 Add "write_smt2 -stbv" 2017-02-24 18:24:53 +01:00
Clifford Wolf a9c3acf5a2 Add SMT2 statebv mode (inactive for now) 2017-02-24 14:04:52 +01:00
Johann Klammer 6d7a77dbf6 Did as you requested, /but/... 
Now the nets are wired in reverse again because the netlister still uses zero-based indices.
 2017-02-24 13:18:49 +01:00
Johann Klammer 06df86aae3 add options for edif flavors 
*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices
 2017-02-23 19:42:37 +01:00
Clifford Wolf 242c5f01de Add "yosys-smtbmc -S <opt>" 2017-02-19 22:51:29 +01:00
Clifford Wolf 4e80ce97a8 Add warning about x/z bits left unconnected in EDIF output 2017-02-14 12:49:35 +01:00
Adam Izraelevitz 794cec0016 More progress on Firrtl backend. 
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
 2017-02-13 11:17:53 -08:00
Clifford Wolf 5541b42159 Add assert check in "yosys-smtbmc -c" 2017-02-04 21:22:17 +01:00
Clifford Wolf adbecfee66 Improve yosys-smtbmc cover() support 2017-02-04 21:10:24 +01:00
Clifford Wolf 0c0784b6bf Partially implement cover() support in yosys-smtbmc 2017-02-04 18:17:08 +01:00
Clifford Wolf 6abf79eb28 Further improve cover() support 2017-02-04 17:02:13 +01:00
Clifford Wolf 18ea65ef04 Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" support 2017-01-30 11:38:43 +01:00
Clifford Wolf e54c355b41 Add "yosys-smtbmc --aig-noheader" and AIGER mem init support 2017-01-28 15:15:02 +01:00
Clifford Wolf b7cfb7dbd2 Fix $initstate handling bug in yosys-smtbmc 2017-01-11 14:14:12 +01:00
Clifford Wolf b9ad91b93e Implicitly set "yosys-smtbmc --noprogress" on windows 2017-01-04 15:23:48 +01:00
Clifford Wolf ed812ea39c Fixed "yosys-smtbmc --noprogress" 2017-01-04 12:03:04 +01:00
Clifford Wolf 81bb952e5d Handle "always 1" like "always -1" in .smtc files 2017-01-02 20:08:03 +01:00
Clifford Wolf 2198948398 Improved write_json help message 2016-12-29 12:13:29 +01:00
Clifford Wolf a61c88f122 Added $anyconst support to AIGER back-end 2016-12-11 13:48:18 +01:00
Clifford Wolf a44cc7a3d1 Added $assert/$assume support to AIGER back-end 2016-12-03 13:20:29 +01:00
Clifford Wolf 37760541bd Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig 2016-12-03 12:37:20 +01:00
Clifford Wolf 88b9733253 Added "yosys-smtbmc --aig" 2016-12-01 13:16:57 +01:00
Clifford Wolf 52c243cf05 Added support for partially initialized regs to smt2 back-end 2016-12-01 12:00:00 +01:00
Clifford Wolf 5fa1fa1e6f Added "write_aiger -zinit -symbols -vmap" 2016-12-01 11:04:36 +01:00
Clifford Wolf c1f762ca56 Added "write_aiger" command 2016-11-30 21:30:24 +01:00
Clifford Wolf df2e5aad6f Bugfix in smt2 back-end for pure checker modules 2016-11-28 15:15:09 +01:00
Clifford Wolf c17d98f55c Removed shebang line from smtio.py, fixes #279 2016-11-27 12:11:04 +01:00
Clifford Wolf 5c2c78e2dd Added wire start_offset and upto handling BLIF back-end 2016-11-23 13:54:33 +01:00
Clifford Wolf f257ccf22e Added "yosys-smtbmc --append" 2016-11-22 21:21:13 +01:00
Adam Izraelevitz f77dc3bacc Bugfix: include assign to write-mask 2016-11-18 11:49:26 -08:00
Clifford Wolf e01382739d More progress in FIRRTL back-end 2016-11-18 02:41:29 +01:00
Clifford Wolf c051115e03 Progress in FIRRTL back-end 2016-11-18 00:32:35 +01:00
Clifford Wolf 57966a619f Added first draft of FIRRTL back-end 2016-11-17 23:36:47 +01:00
Clifford Wolf ce132cf652 Cleanups and fixed in write_verilog regarding reg init 2016-11-16 12:00:39 +01:00
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf caa2fc62ef Adde "write_verilog -renameprefix -v" 2016-11-01 11:30:27 +01:00
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf 281a977b39 Ignore L_pi nets in "yosys-smtbmc --cex" 2016-10-18 10:54:53 +02:00
Clifford Wolf 9e980a2bb0 Use init value "2" for all uninitialized FFs in BLIF back-end 2016-10-18 10:54:04 +02:00
Clifford Wolf 0bcc617a4f Added "yosys-smtbmc --cex <filename>" 2016-10-17 14:57:28 +02:00
Clifford Wolf 189fbd4cf8 cleanup in write_smt2 log messages (-bv and -mem are now default) 2016-10-16 23:02:51 +02:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 11130d581d Merge branch 'master' of github.com:cliffordwolf/yosys 2016-10-11 03:58:27 +02:00
Clifford Wolf 5f6a838823 Added smtc support for top-level state with [], [N:] syntax 2016-10-08 12:25:34 +02:00
Clifford Wolf 5f7c5e685b Bugfix in yosys-smtbmc --noincr 2016-10-04 00:54:44 +02:00
Clifford Wolf 1114ce9210 yosys-smtbmc: ABC is a QF_BV solver 2016-10-03 20:43:38 +02:00
Clifford Wolf 99b2093bc4 Added "yosys-smtbmc --noincr" 2016-10-03 20:30:38 +02:00
Clifford Wolf 9aec8a1672 yosys-smtbmc: added smtc [...] support for cells 2016-10-02 22:08:30 +02:00
Clifford Wolf 4eb0d6fc0e Added "yosys-smtbmc -s abc" 2016-10-01 13:54:21 +02:00
Clifford Wolf 34e2fb594d Minor improvements in yosys-smtbmc 2016-09-24 20:40:22 +02:00
Clifford Wolf 2e244c2d8e Added yosys-smtbmc --noinfo and --dummy 2016-09-19 20:43:28 +02:00
Clifford Wolf d009cdd6ee Improved handling of SMT2 logics in yosys-smtbmc 2016-09-18 20:48:09 +02:00
Clifford Wolf 7bc88e8101 yosys-smtbmc: added -i support smtc files 2016-09-18 00:48:36 +02:00
Clifford Wolf d39db41df8 Work-around for boolector bug 2016-09-13 13:23:06 +02:00
Clifford Wolf 6f416c1953 Added missing :produce-models setting to smtio.py 2016-09-11 18:17:22 +02:00
Clifford Wolf 5199aafca0 Minor improvements to smtio.py vcd writer 2016-09-10 16:24:08 +02:00
Clifford Wolf b582f11074 fixed write_smt2 for (non-combinatorial) loops through hierarchical cells 2016-09-10 15:14:41 +02:00
Clifford Wolf 3ceba145d5 smt2 mem init bugfix 2016-09-08 18:08:15 +02:00
Clifford Wolf 14bfd3c5c1 yosys-smtbmc meminit support 2016-09-08 11:16:12 +02:00
Clifford Wolf 209a3d9ffc Bugfix in "yosys-smtbmc --unroll" 2016-09-07 21:01:51 +02:00
Clifford Wolf 6770d6e0f8 Added "yosys-smtbmc --unroll" 2016-09-07 20:57:56 +02:00
Clifford Wolf 97b449fe55 yosys-smtbmc: flush stdout after each log msg 2016-09-06 01:40:31 +02:00
Clifford Wolf 372d672c2a Minor bugfix in write_smt2 2016-09-04 16:32:47 +02:00
Clifford Wolf fa5565b606 Added boolector support to yosys-smtbmc 2016-09-03 14:26:00 +02:00
Clifford Wolf 948aac9e1e Don't re-create hex_dict for each value 2016-09-02 13:46:56 +02:00
Kaj Tuomi d88cd0ae7f More PEP 8 fixes. 2016-09-02 13:09:09 +03:00
Kaj Tuomi c4ba1965fd Indentation and PEP 8 fixes. CamelCase and white space after semicolon. 2016-09-02 13:01:31 +03:00
Kaj Tuomi 2343dda946 Use dict lookup instead of many ifs. 2016-09-02 12:50:23 +03:00
Kaj Tuomi 279298c0b8 Fix: Unresolved reference. 2016-09-02 11:12:30 +03:00
Kaj Tuomi 74dd36ad55 Some syntax fixes. Generator and comma separated list modifications. 2016-09-02 11:02:19 +03:00
Clifford Wolf aa25a4cec6 Added $anyconst support to yosys-smtbmc 2016-08-30 19:27:42 +02:00
Clifford Wolf a8124c137e Fixed memory bug in write_smt2 2016-08-30 14:49:47 +02:00
Clifford Wolf b04a40d9fe Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem" 2016-08-30 12:40:09 +02:00
Clifford Wolf 39e4faa2e4 Added $anyconst support to smt2 back-end 2016-08-30 11:26:10 +02:00
Clifford Wolf c417421495 Added "yosys-smtbmc --dump-all" 2016-08-29 22:41:45 +02:00
Clifford Wolf b226893461 More yosys-smtbmc bugfixes 2016-08-29 14:53:32 +02:00
Clifford Wolf a2e2fc5980 Various fixes and improvements in yosys-smtbmc 2016-08-29 13:53:12 +02:00
Clifford Wolf f56dba8e20 Some changes to yosys-smtbmc cmd line options, add --final-only 2016-08-27 22:04:15 +02:00
Clifford Wolf adcda6817e Added smtc "final" statement 2016-08-27 14:30:36 +02:00
Clifford Wolf 17233b11e1 Various fixes and improvements in smt2 back-end 2016-08-26 17:33:02 +02:00
Clifford Wolf ad56ad44c3 More yosys-smtbmc smtc features 2016-08-24 23:18:29 +02:00
Clifford Wolf ee3e7a0e45 yosys-smtbmc --smtc -g 2016-08-24 22:09:50 +02:00
Clifford Wolf 6523023645 Minor yosys-smtbmc bugfix 2016-08-22 17:45:01 +02:00
Clifford Wolf 583ceee6eb Added "yosys-smtbmc --constr" 2016-08-22 17:27:43 +02:00
Clifford Wolf 2bd30e2026 Added "yosys-smtbmc --dump-constr" 2016-08-22 16:48:46 +02:00
Clifford Wolf 7a33b9892a yosys-smtbmc: improved --dump-vlogtb handling of memories 2016-08-21 15:56:22 +02:00
Clifford Wolf f7578b0239 Added "yosys-smtbmc --dump-vlogtb" 2016-08-20 18:43:39 +02:00
Clifford Wolf ed785194de Added support for memories to smtio.py 2016-08-20 18:42:32 +02:00
Clifford Wolf c325bae792 Deprecated "write_smt2 -regs" (by default on now), and some other smt2 back-end improvements 2016-08-20 18:41:57 +02:00
Clifford Wolf 28271e43c9 Added "yosys-smtbmc -g" 2016-08-20 16:32:50 +02:00
Clifford Wolf a889acb897 Added smtbmc longopt support 2016-08-20 16:07:59 +02:00
Clifford Wolf 75bf7416f0 Bugfix in partial mem write handling in verilog back-end 2016-08-20 13:06:06 +02:00
Clifford Wolf 9b8e06bee1 Added missing support for mem read enable ports to verilog back-end 2016-08-18 21:47:02 +02:00
Clifford Wolf de8ee412c3 Improved smtbmc vcd generation performance 2016-08-18 11:17:45 +02:00
Clifford Wolf dfcd30ea86 Added printing of code loc of failed asserts to yosys-smtbmc 2016-08-17 20:10:02 +02:00
Clifford Wolf f0a8713fea Fixed upto handling in verilog back-end 2016-08-15 08:26:20 +02:00
Clifford Wolf 21e1bac084 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-07-30 12:50:39 +02:00
Clifford Wolf 5fe13a16ea Added "write_verilog -defparam" 2016-07-30 12:46:06 +02:00
Clifford Wolf 7fa61cba1b Added "write_verilog -nodec -nostr" 2016-07-30 12:38:40 +02:00
Clifford Wolf da56a5bbc6 Added $initstate support to smtbmc flow 2016-07-27 16:11:37 +02:00
whitequark 546233f0e1 write_json: also write module attributes. 2016-07-12 06:32:04 +00:00
Clifford Wolf c71785d65e Yosys-smtbmc: Support for hierarchical VCD dumping 2016-07-11 12:49:33 +02:00
Clifford Wolf 0153ad85d9 Moved smt2 yosys info parsing from smtbmc.py to smtio.py 2016-07-11 11:49:05 +02:00
Clifford Wolf 771c5fe000 Support for hierarchical designs in smt2 back-end 2016-07-10 18:11:25 +02:00
Clifford Wolf 27b5347a87 Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior 2016-07-08 11:51:04 +02:00
Clifford Wolf 72149aba2e In BLIF, a .names without entries already always outputs 0 2016-07-08 11:41:26 +02:00
Clifford Wolf f6b7cf23d6 Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr 2016-07-08 11:32:36 +02:00
Clifford Wolf 5ffad4e073 Added $sop support to BLIF back-end 2016-06-18 12:28:49 +02:00
Clifford Wolf f3983a0940 Also escape "=" in spice output 2016-05-20 16:43:13 +02:00
Clifford Wolf d10dfccabb Added "write_blif -noalias" 2016-05-06 15:05:53 +02:00
Clifford Wolf 60ac1bd178 Added support for "active high" and "active low" latches in BLIF back-end 2016-04-22 18:00:46 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 3920bf58d0 Fixed some typos 2016-04-05 08:18:21 +02:00
Clifford Wolf 1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Clifford Wolf 2a8d5e64f5 Bugfix in write_verilog for RTLIL processes 2016-03-14 13:03:28 +01:00
Clifford Wolf d117893007 Added "write_edif -nogndvcc" 2016-03-08 21:30:45 +01:00
Clifford Wolf 5547fae4cf Be more conservative with net names in spice output 2016-03-02 12:02:59 +01:00
Sebastian Kuzminsky 7e6426a67d user-facing spelling fixes 
"speciefied" -> "specified"
"unkown" -> "unknown"
 2016-02-28 15:14:01 -07:00
Clifford Wolf 0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf 4393a8ffbf Added "write_blif -cname" mode 2016-01-06 14:32:28 +01:00
Clifford Wolf 47fac573cf Added yosys-smtbmc -S 2015-12-20 09:58:54 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf 255bb914ba Progress in yosys-smtbmc 2015-10-15 15:54:59 +02:00
Clifford Wolf 302166dd59 Improvements in yosys-smtbmc 2015-10-15 15:10:33 +02:00
Clifford Wolf 5dd3e93e8f More "yosys-smtbmc -c" fixes 2015-10-14 23:23:25 +02:00
Clifford Wolf 9fd0f87059 Fixed yosys-smtbmc -c 2015-10-14 23:00:46 +02:00
Clifford Wolf 3c31572152 Added yosys-smtbmc copyright 2015-10-14 01:31:54 +02:00
Clifford Wolf d7de0f4bd1 Improvements in yosys-smtbmc 2015-10-14 01:27:55 +02:00
Clifford Wolf 821f1b8534 Added yosys-smtbmc 2015-10-14 00:47:04 +02:00
Clifford Wolf 7bcd2a4bb3 Implemented smtbmc.py -i 2015-10-14 00:18:38 +02:00
Clifford Wolf 29160525aa Added smtbmc.py 2015-10-13 17:17:23 +02:00
Clifford Wolf 3a22b31bda Added write_smt2 -wires 2015-10-13 17:17:12 +02:00
Clifford Wolf 4ac202e2a5 Bugfixes in writing of memories as Verilog 2015-09-25 13:49:26 +02:00
Clifford Wolf 09b51cb375 Added "yosys-smt2-wire" tag support to smt2 back-end 2015-08-31 02:05:58 +02:00
Clifford Wolf b659ffb457 Fixed generation of smt2 concat statements 2015-08-15 11:45:44 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 698357dd9a Added "write_smt2 -regs" 2015-08-12 17:13:54 +02:00
Clifford Wolf f81bf9bdea Added SMV back-end 'test_cells.sh' script 2015-08-12 12:56:20 +02:00
Clifford Wolf 883e09d8ed Use MEMID as name for $mem cell 2015-08-09 13:35:44 +02:00
Clifford Wolf 6834461f65 Remove some very strange whitespace in btor.cc (by Larry Doolittle) 2015-08-05 22:11:26 +02:00
Clifford Wolf 5dc23975eb Bugfix in SMV back-end for partially unassigned wires 2015-08-05 11:36:26 +02:00
Clifford Wolf c7fd3fbb68 Added $assert support to SMV back-end 2015-08-04 20:05:37 +02:00
Clifford Wolf eac0bcd7d3 Improvements in BLIF back-end 2015-07-29 17:06:19 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 3123c45415 Added init support to SMV back-end 2015-06-19 16:43:02 +02:00
Clifford Wolf 6c6bf4999e Progress in SMV back-end 2015-06-19 16:26:53 +02:00
Clifford Wolf 8c79765de5 Progress in SMV back-end 2015-06-19 14:08:46 +02:00
Clifford Wolf 8a86162ae9 Progress in SMV back-end 2015-06-18 16:29:11 +02:00
Clifford Wolf 8e84418225 Progress in SMV back-end 2015-06-17 09:56:42 +02:00
Clifford Wolf 9f7a5b4ef9 Progress in SMV back-end 2015-06-17 07:24:27 +02:00
Clifford Wolf b8c5e27006 Progress in SMV back-end 2015-06-16 19:05:26 +02:00
Clifford Wolf 52315039c5 Progress in SMV back-end 2015-06-15 17:01:01 +02:00
Clifford Wolf 0f01ef61ef Progress in SMV back-end 2015-06-15 13:24:17 +02:00
Clifford Wolf ea23bb8aa4 Added "write_smv" skeleton 2015-06-15 00:46:27 +02:00
Clifford Wolf 93685a77c6 Removed debug code from write_smt2 2015-06-14 16:22:06 +02:00
Clifford Wolf 255dcb27a0 Added write_smt2 -mem 2015-06-14 15:46:47 +02:00
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf 3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" 2015-06-11 10:48:16 +02:00
Clifford Wolf 1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf e534881794 Added "json -aig" 2015-06-10 08:13:56 +02:00
luke whittlesey 2f90499e3d $mem cell in verilog backend : grouped writes by clock 2015-06-08 17:35:40 -04:00
luke whittlesey a8fe040906 Bug fix in $mem verilog backend + changed tests/bram flow of make test. 2015-06-04 16:12:40 -04:00
Clifford Wolf 08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf 4744bb95fb Some fixes for $mem in verilog back-end 2015-05-20 13:55:50 +02:00
Clifford Wolf 42348cddd9 Merge pull request #63 from wluker/verilog-backend-mem 
Fixed bug in $mem cell verilog code generation.
 2015-05-11 21:38:06 +02:00
luke whittlesey 3bb5f064b8 Fixed bug in $mem cell verilog code generation. 2015-05-11 14:05:18 -04:00
Clifford Wolf 9e56739634 Disabled broken $mem support in verilog backend 2015-05-10 21:38:41 +02:00
luke whittlesey 6de8fea2c7 Made changes recommended by Clifford Wolf ... 
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
 2015-05-10 11:33:24 -04:00
luke whittlesey 2c1e150297 Verilog backend for $mem cells should now be able to handle different 
write-enable bits and RD_TRANSPARENT parameter settings.
 2015-05-08 15:29:51 -04:00
luke whittlesey c0b68f4848 Added support for $mem cells in the verilog backend. 2015-05-07 13:03:09 -04:00
eddiehung 7c62318239 Fix for all zero mask 2015-05-03 12:53:09 +01:00
eddiehung 079c1205fe Escape '<' and '>' some more 2015-05-03 10:37:20 +01:00
eddiehung 872e13321c For vtr, escape angle brackets as well 2015-04-28 08:56:00 +01:00
eddiehung 058deb777e blifwriter: write out .names for true/false/undef type == '-' 2015-04-28 08:55:26 +01:00
Clifford Wolf d176e613c2 Minor fixes in handling of "init" attribute 2015-04-09 15:12:26 +02:00
Clifford Wolf aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) 2015-04-08 12:13:53 +02:00
Clifford Wolf c0e2b3eb11 Added "port_directions" to write_json output 2015-04-06 01:49:58 +02:00
Clifford Wolf b0c0ede879 Added "init" attribute support to verilog backend 2015-04-04 18:06:52 +02:00
Ahmed Irfan 13e2e71ebe Update README 
corrected url
 2015-04-03 17:11:45 +02:00
Ahmed Irfan ed750f0a55 Delete btor.ys 
.ys script not needed
 2015-04-03 16:45:54 +02:00
Ahmed Irfan e82e4f7df4 Update README 
pmux cell is implemented
 2015-04-03 16:45:14 +02:00
Ahmed Irfan ea2e0297d5 separated memory next from write cell 2015-04-03 16:41:50 +02:00
Clifford Wolf 67e6dcd34a Added Verilog backend $dffsr support 2015-03-18 08:01:37 +01:00
Clifford Wolf 6c8fdb1829 Documentation for JSON format, added attributes 2015-03-06 10:21:21 +01:00
Clifford Wolf adc12ce46e Json bugfix 2015-03-03 09:41:41 +01:00
Clifford Wolf 4fc63f27a1 Json backend improvements 2015-03-03 09:28:44 +01:00
Clifford Wolf 795a6e1d04 Added write_blif -attr 2015-03-02 23:47:45 +01:00
Clifford Wolf 8b488983d0 Added JSON backend 2015-03-02 23:30:58 +01:00
Clifford Wolf 5d4f513c3b Added $assume support to write_smt2 2015-02-26 19:02:55 +01:00
Clifford Wolf ff3f2448b1 Minor "write_smt2" help msg change 2015-02-22 16:30:02 +01:00
Clifford Wolf 4b89dd983c Added "<mod>_a" and "<mod>_i" to write_smt2 output 2015-02-22 16:19:10 +01:00
Clifford Wolf 756b4064b2 Fixed "write_verilog -attr2comment" handling of "*/" in strings 2015-02-13 22:48:10 +01:00
Clifford Wolf 6978f3a77b Added EDIF backend support for multi-bit cell ports 2015-02-01 15:43:35 +01:00
Clifford Wolf fb8c755726 Shorter "dump" options 2015-01-31 23:52:36 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf 146f769bee Cosmetic changes in verilog output format 2015-01-02 22:57:08 +01:00
Clifford Wolf eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf e8c12e5f0c Various fixes and improvements in "write_smt2 -bv" 2014-12-25 20:28:34 +01:00
Clifford Wolf 68233baa1f Various fixes and improvements in write_smt2 2014-12-25 17:52:31 +01:00
Clifford Wolf 95f17dbab0 Added support for most BV cell types to write_smt2 2014-12-25 15:37:02 +01:00
Clifford Wolf 1c3d51375f Added "write_smt2 -bv" and other write_smt2 improvements 2014-12-25 13:30:20 +01:00
Clifford Wolf e548483c91 Added write_smt2 (only gate level logic supported so far) 2014-12-24 16:17:57 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 5df192e71c Added $dffe support to write_verilog 2014-12-20 00:03:20 +01:00
Clifford Wolf 30de490d86 Fixed another bug in write_blif handling of $lut cells 2014-12-19 17:54:44 +01:00
Clifford Wolf b95051fb70 Fixed writing of $lut cells in BLIF backend 2014-12-17 11:13:57 +01:00
Clifford Wolf e01254d824 Added "write_blif -undef" and support for special "-" true/false/undef type 2014-12-14 18:00:38 +01:00
Clifford Wolf 59d11978fc Added "write_blif -blackbox" 
based on code by Eddie Hung from
https://github.com/eddiehung/yosys/commit/1e481661cb4a4
 2014-12-14 17:45:03 +01:00
Clifford Wolf 32dce4a870 Added "blif -unbuf" feature 2014-12-14 17:37:46 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf 461594bb83 Fixed generation of temp names in verilog backend 2014-11-07 14:40:06 +01:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Ahmed Irfan d3c67ad9b6 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc
 2014-09-22 11:35:04 +02:00
Clifford Wolf 309623ff17 Sorting of object names in ilang backend 2014-09-19 15:50:34 +02:00
ahmedirfan1983 b783dbe148 fixed memory next issue, when same memory is written in different case statement 
fixed reduce_xnor, logic_not bug translation bug
 2014-09-18 11:19:48 +02:00
Clifford Wolf 9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf b9cb483f3e Using $pos models for $bu0 2014-09-03 21:20:59 +02:00
Ahmed Irfan 2446b6fbef added $pmux cell translation 2014-09-02 14:47:51 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf f82c978e08 Fixed AOI/OAI expr handling in verilog backend 2014-08-16 22:05:09 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 88cf00ce78 Be more conservative with printing decimal numbers in verilog backend 2014-08-02 21:54:02 +02:00
Clifford Wolf ca1b5d50e0 Improved verilog output for ordinary $mux cells 2014-08-02 21:10:08 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 4147b55c23 Added "autoidx" statement to ilang file format 2014-07-21 15:15:18 +02:00
Clifford Wolf a30e2857c7 Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend 2014-07-20 02:16:30 +02:00
Clifford Wolf 0c67393313 Added support for $bu0 to verilog backend 2014-07-20 01:56:16 +02:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf f7bd0a5232 Use log_abort() and log_assert() in BTOR backend 2014-03-07 15:56:10 +01:00
Clifford Wolf 337b461d26 Added $lut support to blif backend (by user eddiehung from reddit) 2014-02-22 14:25:32 +01:00
Clifford Wolf 038eac7414 Better handling of nameDef and nameRef in edif backend 2014-02-21 13:40:43 +01:00
Clifford Wolf f3ff29d410 Fixed instantiating multi-bit ports in edif backend 2014-02-21 13:10:36 +01:00
Clifford Wolf 79f8944811 Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param 2014-02-21 10:40:15 +01:00
Ahmed Irfan ac896c63e2 modified btor synthesis script for correct use of splice command. 2014-02-12 13:38:28 +01:00
Ahmed Irfan 45e468114a disabling splice command in the script 2014-02-11 15:43:03 +01:00
Ahmed Irfan 1d64b3e008 register output corrected 2014-02-11 13:28:05 +01:00
Ahmed Irfan e8f6b8f201 added concat and slice cell translation 2014-02-11 13:06:01 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf f4f230d7cc Fixed gcc compiler warnings with release build 2014-02-06 22:49:14 +01:00
Clifford Wolf 583636f0ad Added BTOR backend README file 2014-02-05 18:31:10 +01:00
Clifford Wolf 968ae31cac Added support for dump -append 2014-02-04 23:45:30 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf fa103e55ad Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys 2014-01-26 02:29:19 +01:00
Johann Glaser f13b3518aa beautified write_intersynth 2014-01-25 20:16:38 +01:00
Ahmed Irfan 0325efe172 root bug corrected 2014-01-25 19:33:24 +01:00
Ahmed Irfan 137742786e removed regex include 2014-01-24 18:04:37 +01:00
Ahmed Irfan 2e44b1b73a merged clifford changes + removed regex 2014-01-24 17:35:42 +01:00
Clifford Wolf 210dda286f Use techmap -share_map in btor scripts 2014-01-24 15:52:16 +01:00
Clifford Wolf 6804edd5d4 Moved btor scripts to backends/btor/ 2014-01-24 15:48:07 +01:00
Ahmed Irfan aa3cb20e1e slice bug corrected 2014-01-20 18:35:52 +01:00
Ahmed Irfan c347f2825f assert feature 2014-01-20 10:45:02 +01:00
Ahmed Irfan 9a689f33a5 verilog default options pull 
shift operator width issues
 2014-01-17 19:32:35 +01:00
Ahmed Irfan c7a2e582aa slice error corrected 2014-01-16 20:16:01 +01:00
Ahmed Irfan 3a1490888d width issues 
dff cell for more than one registers
 2014-01-15 17:36:33 +01:00
Ahmed Irfan 661b5a993e BTOR backend 2014-01-14 12:03:53 +01:00
Ahmed Irfan 06482c046b Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-03 10:54:54 +01:00
Ahmed Irfan ffd768ce86 btor 2014-01-03 10:52:44 +01:00
Clifford Wolf 74d0de3b74 Updated manual/command-reference-manual.tex 2013-12-28 12:14:47 +01:00
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf b5afd75b0a Fixed gentb_constant handling in autotest backend 2013-12-04 09:09:42 +01:00
Clifford Wolf ed441346ca Added dump -m and -n options 2013-11-29 10:33:36 +01:00
Clifford Wolf 41205afc39 Added proper dumping of signed/unsigned parameters to verilog backend 2013-11-24 17:47:22 +01:00
Clifford Wolf 0ef22c7609 Added support for signed parameters in ilang 2013-11-24 17:37:27 +01:00
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf 1e6836933d Added modelsim support to autotest 2013-11-24 15:10:43 +01:00
Clifford Wolf 28093d9dd2 Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
Clifford Wolf 40d9542647 Implemented $_DFFSR_ expression generator in verilog backend 2013-11-21 21:52:30 +01:00
Clifford Wolf 09471846c5 Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
Clifford Wolf 2864cb3b59 Silenced a gcc warning in spice backend 2013-11-09 12:01:50 +01:00
Clifford Wolf ba305a7ca6 Improved comments on topological sort in edif backend 2013-11-04 08:34:15 +01:00
Clifford Wolf cd0fe7d786 Added simple topological sort to edif backend 2013-11-03 22:01:32 +01:00
Clifford Wolf 1dcb683fcb Write yosys version to output files 2013-11-03 21:41:39 +01:00
Clifford Wolf eab536a203 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-11-03 21:13:21 +01:00
Clifford Wolf 4a60e5842d Ignore explicit unconnected ports in intersynth backend 2013-11-03 09:00:51 +01:00
Clifford Wolf 0efe16f118 Added placeholder check to dfflibmap and cleaned up some other placeholder checks 2013-10-31 12:27:07 +01:00
Clifford Wolf d9fa1e5a1d Fixed hex string generation bug in edif backend 2013-10-27 08:21:05 +01:00
Clifford Wolf 628b994cf6 Added support for complex set-reset flip-flops in proc_dff 2013-10-24 16:54:05 +02:00
Clifford Wolf e9dede01ca Fixed handling of boolean attributes (backends) 2013-10-24 11:27:30 +02:00
Clifford Wolf eae43e2db4 Fixed handling of boolean attributes (kernel) 2013-10-24 10:59:27 +02:00
Clifford Wolf e0f693cbb0 Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ 2013-10-18 12:13:34 +02:00
Clifford Wolf 5998c101a4 Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
Clifford Wolf 30b0de006f Added -buf, -true and -false options to blif backend 2013-10-17 21:37:18 +02:00
Clifford Wolf 5dce6379aa Improvements in EDIF backend 2013-09-17 13:07:12 +02:00
Clifford Wolf dc767d4e4c Added additional options to BLIF backend 2013-09-15 13:33:33 +02:00
Clifford Wolf 0ec5542ab4 Added BLIF backend 2013-09-15 13:13:01 +02:00
Clifford Wolf 28069e8a10 A couple of small fixes in SPICE backend 2013-09-15 12:19:06 +02:00
Clifford Wolf 2c9bd23801 Added spice testbench to techlibs/cmos 2013-09-14 13:29:11 +02:00
Clifford Wolf bbe5aa446b Added spice backend 2013-09-14 11:23:45 +02:00
Clifford Wolf 70476e2431 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-09-03 19:10:25 +02:00
Clifford Wolf 73914d1a41 Added -selected option to various backends 2013-09-03 19:10:11 +02:00
Clifford Wolf 09e200797a Encode large (>32 bits) parameters as hex string in edif backend 2013-08-28 08:48:49 +02:00
Clifford Wolf 2feee7415d Improved edif backend 2013-08-27 14:22:11 +02:00
Clifford Wolf 39ee561169 More explicit integer output in verilog backend 2013-08-22 20:31:04 +02:00
Clifford Wolf 4f4cb2307f Added correct encoding of identifiers in EDIF backend 2013-08-22 14:30:33 +02:00
Clifford Wolf aba8639a3f Added edif backend (still under construction) 2013-08-22 11:34:55 +02:00
Clifford Wolf af79b4bd98 Fixed generation of newlines in "dump" output 2013-06-10 12:38:02 +02:00
Clifford Wolf 21d9251e52 Added "dump" command (part ilang backend) 2013-06-02 17:53:30 +02:00
Clifford Wolf 7bfc7b61a8 Implemented proper handling of stub placeholder modules 2013-03-28 09:20:10 +01:00
Clifford Wolf 05ae20f260 Added -notypes option to intersynth backend 2013-03-24 12:05:25 +01:00
Clifford Wolf a0fa259d81 Fixed gcc build (intersynth backend) 2013-03-23 19:01:58 +01:00
Clifford Wolf bee57c808a Various improvements in intersynth backend 2013-03-23 12:02:09 +01:00
Clifford Wolf 80aefb3eaa Added intersynth backend 2013-03-23 10:58:14 +01:00
Clifford Wolf 87c7717566 Avoid verilog-2k in verilog backend 2013-03-21 09:51:25 +01:00
Clifford Wolf 11789db206 More support code for $sr cells 2013-03-14 11:15:00 +01:00
Clifford Wolf 441e5fbfca Fixed a gcc compiler warning [-Wparentheses] 2013-03-03 22:45:06 +01:00
Clifford Wolf 7fccad92f7 Added more help messages 2013-03-01 00:36:19 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00