mirror of https://github.com/YosysHQ/yosys.git
Progress in SMV back-end
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@ -38,6 +38,7 @@ struct SmvWorker
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int idcounter;
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dict<IdString, shared_str> idcache;
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pool<shared_str> used_names;
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vector<shared_str> strbuf;
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const char *cid()
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{
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@ -54,16 +55,23 @@ struct SmvWorker
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{
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if (!idcache.count(id))
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{
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string name = log_id(id);
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string name = stringf("_%s", id.c_str());
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if (name.substr(0, 2) == "_\\")
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name = "_" + name.substr(2);
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for (auto &c : name) {
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if (c == '|' || c == '$' || c == '_') continue;
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if (c >= 'a' && c <='z') continue;
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if (c >= 'A' && c <='Z') continue;
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if (c >= '0' && c <='9') continue;
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if (precache) return nullptr;
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c = '_';
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c = '#';
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}
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if (name == "_main")
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name = "main";
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while (used_names.count(name))
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name += "_";
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@ -92,7 +100,7 @@ struct SmvWorker
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}
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}
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string rvalue(SigSpec sig)
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const char *rvalue(SigSpec sig)
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{
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string s;
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sigmap.apply(sig);
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@ -109,11 +117,15 @@ struct SmvWorker
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s += c.data.at(i) == State::S1 ? '1' : '0';
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}
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}
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return s;
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strbuf.push_back(s);
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return strbuf.back().c_str();
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}
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string lvalue(SigSpec sig)
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const char *lvalue(SigSpec sig)
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{
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sigmap.apply(sig);
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if (sig.is_wire())
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return rvalue(sig);
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@ -132,13 +144,79 @@ struct SmvWorker
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for (auto cell : module->cells())
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{
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if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$and", "$or", "$xor", "$xnor"))
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{
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int width = GetSize(cell->getPort("\\Y"));
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string expr_a, expr_b, op;
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if (cell->type == "$add") op = "+";
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if (cell->type == "$sub") op = "-";
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if (cell->type == "$mul") op = "*";
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if (cell->type == "$div") op = "/";
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if (cell->type == "$mod") op = "%";
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if (cell->type == "$and") op = "&";
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if (cell->type == "$or") op = "|";
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if (cell->type == "$xor") op = "xor";
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if (cell->type == "$xnor") op = "xnor";
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if (cell->getParam("\\A_SIGNED").as_bool())
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{
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expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\A")), width);
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expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\B")), width);
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assignments.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")), expr_a.c_str(), op.c_str(), expr_b.c_str()));
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}
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else
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{
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expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort("\\A")), width);
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expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width);
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assignments.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")), expr_a.c_str(), op.c_str(), expr_b.c_str()));
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}
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continue;
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}
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if (cell->type.in("$eq", "$ne", "$lt", "$le", "$ge", "$gt"))
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{
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int width = std::max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
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string expr_a, expr_b, op;
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if (cell->type == "$eq") op = "=";
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if (cell->type == "$ne") op = "!=";
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if (cell->type == "$lt") op = "<";
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if (cell->type == "$le") op = "<=";
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if (cell->type == "$ge") op = ">=";
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if (cell->type == "$gt") op = ">";
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if (cell->getParam("\\A_SIGNED").as_bool())
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{
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expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\A")), width);
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expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\B")), width);
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}
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else
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{
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expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort("\\A")), width);
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expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width);
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}
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assignments.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
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expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort("\\Y"))));
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continue;
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}
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if (cell->type == "$dff")
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{
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assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort("\\Q")), rvalue(cell->getPort("\\D"))));
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continue;
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}
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f << stringf(" %s : %s;\n", cid(cell->name), cid(cell->type));
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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assignments.push_back(stringf("%s := %s.%s;", lvalue(conn.second).c_str(), cid(cell->name), cid(conn.first)));
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assignments.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(conn.first)));
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else
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assignments.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second).c_str()));
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assignments.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second)));
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}
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f << stringf(" ASSIGN\n");
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