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Added modelsim support to autotest

This commit is contained in:
Clifford Wolf 2013-11-24 15:10:43 +01:00
parent 72b35e0b99
commit 1e6836933d
3 changed files with 37 additions and 8 deletions
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12
backends/autotest/autotest.cc
View File

@ -206,7 +206,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "task %s;\n", idy(mod->name, "print_status").c_str());
fprintf(f, "begin\n");
fprintf(f, "\t$display(\"%%b %%b %%b %%t %%d\", {");
fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {");
if (signal_in.size())
for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
fprintf(f, "%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
@ -268,17 +268,17 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "task %s;\n", idy(mod->name, "print_header").c_str());
fprintf(f, "begin\n");
fprintf(f, "\t$display();\n");
fprintf(f, "\t$display(\"#OUT#\");\n");
for (auto &hdr : header1)
fprintf(f, "\t$display(\" %s\");\n", hdr.c_str());
fprintf(f, "\t$display();\n");
fprintf(f, "\t$display(\"%s\");\n", header2.c_str());
fprintf(f, "\t$display(\"#OUT# %s\");\n", hdr.c_str());
fprintf(f, "\t$display(\"#OUT#\");\n");
fprintf(f, "\t$display(\"#OUT# %s\");\n", header2.c_str());
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
fprintf(f, "task %s;\n", idy(mod->name, "test").c_str());
fprintf(f, "begin\n");
fprintf(f, "\t$display(\"\\n==== %s ====\");\n", idy(mod->name).c_str());
fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str());
fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str());
fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", NUM_ITER);
fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str());

21
tests/simple/hierarchy.v Normal file
View File

@ -0,0 +1,21 @@
(* top *)
module top(a, b, y1, y2, y3, y4);
input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;
submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
endmodule
(* gentb_skip *)
module submod(a, b, y1, y2, y3, y4);
parameter c = 0;
parameter [7:0] d = 0;
input [7:0] a, b;
output [7:0] y1, y2, y3, y4;
assign y1 = a;
assign y2 = b;
assign y3 = c;
assign y4 = d;
endmodule

12
tests/tools/autotest.sh
View File

@ -3,6 +3,7 @@
libs=""
genvcd=false
use_isim=false
use_modelsim=false
verbose=false
keeprunning=false
backend_opts="-noattr -noexpr"
@ -14,10 +15,12 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
( set -ex; gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
fi
while getopts il:wkvrxs: opt; do
while getopts iml:wkvrxs: opt; do
case "$opt" in
i)
use_isim=true ;;
m)
use_modelsim=true ;;
l)
libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";;
w)
@ -69,7 +72,12 @@ create_ref() {
compile_and_run() {
exe="$1"; output="$2"; shift 2
if $use_isim; then
if $use_modelsim; then
altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
/opt/altera/$altver/modelsim_ase/bin/vlib work
/opt/altera/$altver/modelsim_ase/bin/vlog "$@"
/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | grep '#OUT#' > "$output"
elif $use_isim; then
(
set +x
files=( "$@" )