mirror of https://github.com/YosysHQ/yosys.git
Remove some very strange whitespace in btor.cc (by Larry Doolittle)
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5dc23975eb
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6834461f65
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@ -79,8 +79,8 @@ struct BtorDumper
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RTLIL::IdString curr_cell; //current cell being dumped
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std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
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std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write
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BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design), sigmap(module)
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BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design), sigmap(module)
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{
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line_num=0;
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str.clear();
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@ -520,7 +520,7 @@ struct BtorDumper
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bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
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bool l2_signed YS_ATTRIBUTE(unused) = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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log_assert(l1_signed == l2_signed);
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l1_width = l1_width > output_width ? l1_width : output_width;
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@ -554,7 +554,7 @@ struct BtorDumper
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bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
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bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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log_assert(l1_signed == l2_signed);
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l1_width = l1_width > output_width ? l1_width : output_width;
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@ -594,7 +594,7 @@ struct BtorDumper
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//bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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l1_width = pow(2, ceil(log(l1_width)/log(2)));
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
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int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
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int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
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@ -641,7 +641,7 @@ struct BtorDumper
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int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
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int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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if(l1_width >1)
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{
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++line_num;
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@ -830,7 +830,7 @@ struct BtorDumper
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mem = line_num - 1;
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}
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*/
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++line_num;
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++line_num;
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if(polarity)
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str = stringf("%d one 1", line_num);
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else
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