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Write yosys version to output files

This commit is contained in:
Clifford Wolf 2013-11-03 21:41:39 +01:00
parent eab536a203
commit 1dcb683fcb
7 changed files with 13 additions and 9 deletions
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2
backends/blif/blif.cc
View File

@ -293,6 +293,8 @@ struct BlifBackend : public Backend {
}
extra_args(f, filename, args, argidx);
fprintf(f, "# Generated by %s\n", yosys_version_str);
std::vector<RTLIL::Module*> mod_list;
for (auto module_it : design->modules)

4
backends/edif/edif.cc
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@ -17,6 +17,9 @@
*
*/
// [[CITE]] EDIF Version 2 0 0 Grammar
// http://web.archive.org/web/20050730021644/http://www.edif.org/documentation/BNF_GRAMMAR/index.html
#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
@ -151,6 +154,7 @@ struct EdifBackend : public Backend {
fprintf(f, " (edifVersion 2 0 0)\n");
fprintf(f, " (edifLevel 0)\n");
fprintf(f, " (keywordMap (keywordLevel 0))\n");
fprintf(f, " (comment \"Generated by %s\")\n", yosys_version_str);
fprintf(f, " (external LIB\n");
fprintf(f, " (edifLevel 0)\n");

1
backends/ilang/ilang_backend.cc
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@ -364,6 +364,7 @@ struct IlangBackend : public Backend {
extra_args(f, filename, args, argidx);
log("Output filename: %s\n", filename.c_str());
fprintf(f, "# Generated by %s\n", yosys_version_str);
ILANG_BACKEND::dump_design(f, design, selected);
}
} IlangBackend;

5
backends/spice/spice.cc
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@ -172,10 +172,7 @@ struct SpiceBackend : public Backend {
}
extra_args(f, filename, args, argidx);
fprintf(f, "\n");
fprintf(f, "*************************************\n");
fprintf(f, "* SPICE netlist, generated by Yosys *\n");
fprintf(f, "*************************************\n");
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n");
for (auto module_it : design->modules)

4
backends/verilog/verilog_backend.cc
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@ -803,6 +803,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
reset_auto_counter(module);
active_module = module;
fprintf(f, "\n");
for (auto it = module->processes.begin(); it != module->processes.end(); it++)
dump_process(f, indent + " ", it->second, true);
@ -956,6 +957,7 @@ struct VerilogBackend : public Backend {
}
extra_args(f, filename, args, argidx);
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
continue;
@ -964,8 +966,6 @@ struct VerilogBackend : public Backend {
log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
continue;
}
if (it != design->modules.begin())
fprintf(f, "\n");
log("Dumping module `%s'.\n", it->first.c_str());
dump_module(f, "", it->second);
}

3
kernel/driver.cc
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@ -31,9 +31,6 @@
#include "kernel/register.h"
#include "kernel/log.h"
// from kernel/version_*.o (cc source generated from Makefile)
extern const char *yosys_version_str;
bool fgetline(FILE *f, std::string &buffer)
{
buffer = "";

3
kernel/register.h
View File

@ -31,6 +31,9 @@
extern Tcl_Interp *yosys_get_tcl_interp();
#endif
// from kernel/version_*.o (cc source generated from Makefile)
extern const char *yosys_version_str;
// implemented in driver.cc
extern RTLIL::Design *yosys_get_design();
std::string rewrite_yosys_exe(std::string exe);