mirror of https://github.com/YosysHQ/yosys.git
Fixed gentb_constant handling in autotest backend
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@ -124,11 +124,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
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is_clksignal = true;
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}
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}
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if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
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if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
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signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
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} else {
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signal_in[idy("sig", mod->name, wire->name)] = wire->width;
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if (wire->get_bool_attribute("\\gentb_constant"))
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if (wire->attributes.count("\\gentb_constant") != 0)
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signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
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}
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fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
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