mirror of https://github.com/YosysHQ/yosys.git
Add $dlatch support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -897,6 +897,42 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == "$dlatch")
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{
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RTLIL::SigSpec sig_en;
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bool pol_en = false;
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sig_en = cell->getPort("\\EN");
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pol_en = cell->parameters["\\EN_POLARITY"].as_bool();
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std::string reg_name = cellname(cell);
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bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
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if (!out_is_reg_wire) {
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f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
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dump_reg_init(f, cell->getPort("\\Q"));
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f << ";\n";
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}
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f << stringf("%s" "always @*\n", indent.c_str());
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f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!");
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dump_sigspec(f, sig_en);
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f << stringf(")\n");
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f << stringf("%s" " %s = ", indent.c_str(), reg_name.c_str());
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dump_cell_expr_port(f, cell, "D", false);
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f << stringf(";\n");
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if (!out_is_reg_wire) {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort("\\Q"));
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f << stringf(" = %s;\n", reg_name.c_str());
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}
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return true;
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}
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if (cell->type == "$mem")
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{
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RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
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@ -1537,6 +1573,8 @@ struct VerilogBackend : public Backend {
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reg_ct.insert("$dff");
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reg_ct.insert("$adff");
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reg_ct.insert("$dffe");
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reg_ct.insert("$dlatch");
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reg_ct.insert("$_DFF_N_");
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reg_ct.insert("$_DFF_P_");
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