mirror of https://github.com/YosysHQ/yosys.git
Update to .smv backend
Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
This commit is contained in:
Aman Goel
parent
33cb5e05be
commit
90e0938f9a
4
Makefile
4
Makefile
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@ -1,6 +1,6 @@
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CONFIG := clang
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# CONFIG := gcc
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# CONFIG := clang
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CONFIG := gcc
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# CONFIG := gcc-4.8
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# CONFIG := emcc
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# CONFIG := mxe
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@ -42,7 +42,7 @@ struct SmvWorker
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pool<Wire*> partial_assignment_wires;
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dict<SigBit, std::pair<const char*, int>> partial_assignment_bits;
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vector<string> assignments, invarspecs;
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vector<string> inputvars, vars, definitions, assignments, invarspecs;
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const char *cid()
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{
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@ -195,7 +195,7 @@ struct SmvWorker
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return rvalue(sig);
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const char *temp_id = cid();
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f << stringf(" %s : unsigned word[%d]; -- %s\n", temp_id, GetSize(sig), log_signal(sig));
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// f << stringf(" %s : unsigned word[%d]; -- %s\n", temp_id, GetSize(sig), log_signal(sig));
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int offset = 0;
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for (auto bit : sig) {
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@ -210,14 +210,14 @@ struct SmvWorker
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void run()
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{
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f << stringf("MODULE %s\n", cid(module->name));
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f << stringf(" VAR\n");
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for (auto wire : module->wires())
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{
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if (SigSpec(wire) != sigmap(wire))
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partial_assignment_wires.insert(wire);
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f << stringf(" %s : unsigned word[%d]; -- %s\n", cid(wire->name), wire->width, log_id(wire));
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if (wire->port_input)
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inputvars.push_back(stringf("%s : unsigned word[%d]; -- %s", cid(wire->name), wire->width, log_id(wire)));
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if (wire->attributes.count("\\init"))
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assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at("\\init"))));
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@ -232,7 +232,7 @@ struct SmvWorker
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SigSpec sig_a = cell->getPort("\\A");
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SigSpec sig_en = cell->getPort("\\EN");
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invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
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invarspecs.push_back(stringf("(!bool(%s) | bool(%s));", rvalue(sig_en), rvalue(sig_a)));
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continue;
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}
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@ -275,8 +275,8 @@ struct SmvWorker
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const char *b_shr = rvalue_u(sig_b);
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const char *b_shl = cid();
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f << stringf(" %s : unsigned word[%d]; -- neg(%s)\n", b_shl, GetSize(sig_b), log_signal(sig_b));
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assignments.push_back(stringf("%s := unsigned(-%s);", b_shl, rvalue_s(sig_b)));
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// f << stringf(" %s : unsigned word[%d]; -- neg(%s)\n", b_shl, GetSize(sig_b), log_signal(sig_b));
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definitions.push_back(stringf("%s := unsigned(-%s);", b_shl, rvalue_s(sig_b)));
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string expr_shl = stringf("resize(%s << %s[%d:0], %d)", expr_a.c_str(), b_shl, shift_b_width-1, width_y);
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string expr_shr = stringf("resize(%s >> %s[%d:0], %d)", expr_a.c_str(), b_shr, shift_b_width-1, width_y);
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@ -303,7 +303,7 @@ struct SmvWorker
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GetSize(sig_b)-shift_b_width, width_y, expr.c_str());
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}
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assignments.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
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definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
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continue;
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}
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@ -319,12 +319,12 @@ struct SmvWorker
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if (cell->getParam("\\A_SIGNED").as_bool())
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{
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assignments.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")),
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op.c_str(), rvalue_s(cell->getPort("\\A"), width)));
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}
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else
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{
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assignments.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")),
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op.c_str(), rvalue_u(cell->getPort("\\A"), width)));
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}
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@ -346,12 +346,12 @@ struct SmvWorker
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if (cell->getParam("\\A_SIGNED").as_bool())
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{
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assignments.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")),
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rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width)));
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}
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else
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{
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assignments.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
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rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width)));
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}
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@ -370,12 +370,12 @@ struct SmvWorker
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if (cell->getParam("\\A_SIGNED").as_bool())
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{
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assignments.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
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rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width), width_y));
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}
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else
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{
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assignments.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")),
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rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width), width_y));
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}
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@ -407,7 +407,7 @@ struct SmvWorker
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expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width);
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}
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assignments.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
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expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort("\\Y"))));
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continue;
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@ -425,7 +425,7 @@ struct SmvWorker
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if (cell->type == "$reduce_or") expr = stringf("%s != 0ub%d_0", expr_a, width_a);
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if (cell->type == "$reduce_bool") expr = stringf("%s != 0ub%d_0", expr_a, width_a);
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assignments.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
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definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
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continue;
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}
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@ -444,7 +444,7 @@ struct SmvWorker
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if (cell->type == "$reduce_xnor")
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expr = "!(" + expr + ")";
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assignments.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y));
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definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y));
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continue;
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}
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@ -462,7 +462,7 @@ struct SmvWorker
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if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b;
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if (cell->type == "$logic_or") expr = expr_a + " | " + expr_b;
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assignments.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
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definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
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continue;
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}
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@ -474,7 +474,7 @@ struct SmvWorker
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string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a);
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const char *expr_y = lvalue(cell->getPort("\\Y"));
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assignments.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y));
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definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y));
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continue;
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}
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@ -490,12 +490,13 @@ struct SmvWorker
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expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width)));
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expr += rvalue(sig_a);
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assignments.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
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definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
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continue;
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}
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if (cell->type == "$dff")
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{
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vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort("\\Q")), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))));
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assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort("\\Q")), rvalue(cell->getPort("\\D"))));
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continue;
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}
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@ -503,7 +504,7 @@ struct SmvWorker
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if (cell->type.in("$_BUF_", "$_NOT_"))
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{
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string op = cell->type == "$_NOT_" ? "!" : "";
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assignments.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A"))));
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definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A"))));
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continue;
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}
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@ -517,49 +518,49 @@ struct SmvWorker
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if (cell->type.in("$_XNOR_")) op = "xnor";
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if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
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assignments.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
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else
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if (cell->type.in("$_NAND_", "$_NOR_"))
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assignments.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
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else
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assignments.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
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continue;
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}
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if (cell->type == "$_MUX_")
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{
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assignments.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A"))));
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continue;
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}
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if (cell->type == "$_AOI3_")
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{
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assignments.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C"))));
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continue;
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}
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if (cell->type == "$_OAI3_")
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{
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assignments.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C"))));
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continue;
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}
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if (cell->type == "$_AOI4_")
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{
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assignments.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
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continue;
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}
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if (cell->type == "$_OAI4_")
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{
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assignments.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")),
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definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")),
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rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
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continue;
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}
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@ -567,13 +568,13 @@ struct SmvWorker
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if (cell->type[0] == '$')
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log_error("Found currently unsupported cell type %s (%s.%s).\n", log_id(cell->type), log_id(module), log_id(cell));
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f << stringf(" %s : %s;\n", cid(cell->name), cid(cell->type));
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// f << stringf(" %s : %s;\n", cid(cell->name), cid(cell->type));
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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assignments.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(conn.first)));
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definitions.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(conn.first)));
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else
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assignments.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second)));
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definitions.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second)));
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}
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for (Wire *wire : partial_assignment_wires)
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@ -657,7 +658,25 @@ struct SmvWorker
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}
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}
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assignments.push_back(stringf("%s := %s;", cid(wire->name), expr.c_str()));
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definitions.push_back(stringf("%s := %s;", cid(wire->name), expr.c_str()));
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}
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if (!inputvars.empty()) {
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f << stringf(" IVAR\n");
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for (const string &line : inputvars)
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f << stringf(" %s\n", line.c_str());
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}
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if (!vars.empty()) {
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f << stringf(" VAR\n");
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for (const string &line : vars)
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f << stringf(" %s\n", line.c_str());
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}
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if (!definitions.empty()) {
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f << stringf(" DEFINE\n");
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for (const string &line : definitions)
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f << stringf(" %s\n", line.c_str());
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}
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if (!assignments.empty()) {
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