mirror of https://github.com/YosysHQ/yosys.git
Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
This commit is contained in:
Jim Lawson
parent
807b3c7697
commit
fc1c9aa11f
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@ -23,7 +23,11 @@
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#include "kernel/celltypes.h"
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#include "kernel/cellaigs.h"
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#include "kernel/log.h"
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#include <algorithm>
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#include <string>
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#include <regex>
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#include <vector>
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#include <cmath>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -37,6 +41,7 @@ static const FDirection FD_NODIRECTION = 0x0;
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static const FDirection FD_IN = 0x1;
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static const FDirection FD_OUT = 0x2;
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static const FDirection FD_INOUT = 0x3;
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static const int FIRRTL_MAX_DSH_WIDTH_ERROR = 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
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// Get a port direction with respect to a specific module.
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FDirection getPortFDirection(IdString id, Module *module)
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@ -91,6 +96,23 @@ const char *make_id(IdString id)
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return namecache.at(id).c_str();
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}
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static std::vector<string> Tokenize( const string str, const std::regex regex )
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{
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using namespace std;
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std::vector<string> result;
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sregex_token_iterator it( str.begin(), str.end(), regex, -1 );
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sregex_token_iterator reg_end;
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for ( ; it != reg_end; ++it ) {
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if ( !it->str().empty() ) //token could be empty:check
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result.emplace_back( it->str() );
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}
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return result;
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}
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struct FirrtlWorker
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{
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Module *module;
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@ -173,6 +195,26 @@ struct FirrtlWorker
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void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
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{
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std::string cell_type = fid(cell->type);
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std::string instanceOf;
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// If this is a parameterized module, its parent module is encoded in the cell type
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if (cell->type.substr(0, 8) == "$paramod")
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{
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std::string::iterator it;
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for (it = cell_type.begin(); it < cell_type.end(); it++)
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{
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switch (*it) {
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case '\\': /* FALL_THROUGH */
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case '=': /* FALL_THROUGH */
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case '\'': /* FALL_THROUGH */
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case '$': instanceOf.append("_"); break;
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default: instanceOf.append(1, *it); break;
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}
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}
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}
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else
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{
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instanceOf = cell_type;
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}
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std::string cell_name = cellname(cell);
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std::string cell_name_comment;
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@ -182,7 +224,13 @@ struct FirrtlWorker
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cell_name_comment = "";
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// Find the module corresponding to this instance.
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auto instModule = design->module(cell->type);
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wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), cell_type.c_str()));
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// If there is no instance for this, just return.
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if (instModule == NULL)
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{
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log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str());
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return;
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}
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wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceOf.c_str()));
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for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
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if (it->second.size() > 0) {
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@ -194,20 +242,20 @@ struct FirrtlWorker
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std::string source, sink;
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switch (dir) {
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case FD_INOUT:
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log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second));
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log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second));
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case FD_OUT:
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source = firstName;
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sink = secondName;
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break;
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case FD_NODIRECTION:
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log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second));
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log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second));
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/* FALL_THROUGH */
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case FD_IN:
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source = secondName;
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sink = firstName;
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break;
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default:
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log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", log_id(cell_type), log_signal(it->second), dir);
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log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
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break;
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}
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wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sink.c_str(), source.c_str()));
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@ -217,6 +265,20 @@ struct FirrtlWorker
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}
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// Given an expression for a shift amount, and a maximum width,
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// generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
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std::string gen_dshl(const string b_expr, const int b_padded_width)
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{
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string result = b_expr;
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if (b_padded_width >= FIRRTL_MAX_DSH_WIDTH_ERROR) {
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int max_shift_width_bits = FIRRTL_MAX_DSH_WIDTH_ERROR - 1;
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string max_shift_string = stringf("UInt<%d>(%d)", max_shift_width_bits, (1<<max_shift_width_bits) - 1);
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// Deal with the difference in semantics between FIRRTL and verilog
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result = stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr.c_str(), max_shift_string.c_str(), max_shift_string.c_str(), b_expr.c_str(), max_shift_width_bits - 1);
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}
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return result;
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}
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void run()
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{
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f << stringf(" module %s:\n", make_id(module->name));
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@ -225,6 +287,12 @@ struct FirrtlWorker
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for (auto wire : module->wires())
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{
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const auto wireName = make_id(wire->name);
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// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
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if (wire->attributes.count("\\init")) {
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log_warning("Initial value (%s) for (%s.%s) not supported\n",
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wire->attributes.at("\\init").as_string().c_str(),
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log_id(module), log_id(wire));
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}
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if (wire->port_id)
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{
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if (wire->port_input && wire->port_output)
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@ -240,7 +308,8 @@ struct FirrtlWorker
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for (auto cell : module->cells())
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{
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// Is this cell is a module instance?
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bool extract_y_bits = false; // Assume no extraction of final bits will be required.
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// Is this cell is a module instance?
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if (cell->type[0] != '$')
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{
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process_instance(cell, wire_exprs);
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@ -264,21 +333,21 @@ struct FirrtlWorker
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}
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string primop;
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bool always_uint = false;
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bool always_uint = false;
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if (cell->type == "$not") primop = "not";
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if (cell->type == "$neg") primop = "neg";
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if (cell->type == "$logic_not") {
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else if (cell->type == "$neg") primop = "neg";
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else if (cell->type == "$logic_not") {
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primop = "eq";
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a_expr = stringf("%s, UInt(0)", a_expr.c_str());
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}
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if (cell->type == "$reduce_and") primop = "andr";
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if (cell->type == "$reduce_or") primop = "orr";
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if (cell->type == "$reduce_xor") primop = "xorr";
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if (cell->type == "$reduce_xnor") {
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else if (cell->type == "$reduce_and") primop = "andr";
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else if (cell->type == "$reduce_or") primop = "orr";
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else if (cell->type == "$reduce_xor") primop = "xorr";
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else if (cell->type == "$reduce_xnor") {
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primop = "not";
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a_expr = stringf("xorr(%s)", a_expr.c_str());
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}
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if (cell->type == "$reduce_bool") {
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else if (cell->type == "$reduce_bool") {
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primop = "neq";
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// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
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bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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@ -297,14 +366,16 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$and", "$or", "$eq", "$eqx",
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"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
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"$logic_and", "$logic_or"))
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"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
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"$logic_and", "$logic_or"))
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{
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string y_id = make_id(cell->name);
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bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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int y_width = cell->parameters.at("\\Y_WIDTH").as_int();
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string a_expr = make_expr(cell->getPort("\\A"));
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int a_padded_width = cell->parameters.at("\\A_WIDTH").as_int();
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string b_expr = make_expr(cell->getPort("\\B"));
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int b_padded_width = cell->parameters.at("\\B_WIDTH").as_int();
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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if (cell->parameters.at("\\A_SIGNED").as_bool()) {
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@ -315,67 +386,93 @@ struct FirrtlWorker
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if (cell->parameters.at("\\B_SIGNED").as_bool()) {
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b_expr = "asSInt(" + b_expr + ")";
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}
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b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
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if (b_padded_width < y_width) {
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auto b_sig = cell->getPort("\\B");
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b_padded_width = y_width;
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}
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}
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a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
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auto a_sig = cell->getPort("\\A");
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if (cell->parameters.at("\\A_SIGNED").as_bool() & (cell->type == "$shr")) {
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a_expr = "asUInt(" + a_expr + ")";
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}
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string primop;
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bool always_uint = false;
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bool always_uint = false;
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if (cell->type == "$add") primop = "add";
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if (cell->type == "$sub") primop = "sub";
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if (cell->type == "$mul") primop = "mul";
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if (cell->type == "$div") primop = "div";
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if (cell->type == "$mod") primop = "rem";
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if (cell->type == "$and") {
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else if (cell->type == "$sub") primop = "sub";
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else if (cell->type == "$mul") primop = "mul";
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else if (cell->type == "$div") primop = "div";
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else if (cell->type == "$mod") primop = "rem";
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else if (cell->type == "$and") {
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primop = "and";
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always_uint = true;
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}
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if (cell->type == "$or" ) {
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else if (cell->type == "$or" ) {
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primop = "or";
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always_uint = true;
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}
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if (cell->type == "$xor") {
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else if (cell->type == "$xor") {
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primop = "xor";
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always_uint = true;
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}
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if ((cell->type == "$eq") | (cell->type == "$eqx")) {
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else if ((cell->type == "$eq") | (cell->type == "$eqx")) {
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primop = "eq";
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always_uint = true;
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}
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if ((cell->type == "$ne") | (cell->type == "$nex")) {
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else if ((cell->type == "$ne") | (cell->type == "$nex")) {
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primop = "neq";
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always_uint = true;
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}
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if (cell->type == "$gt") {
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else if (cell->type == "$gt") {
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primop = "gt";
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always_uint = true;
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}
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if (cell->type == "$ge") {
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else if (cell->type == "$ge") {
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primop = "geq";
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always_uint = true;
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}
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if (cell->type == "$lt") {
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else if (cell->type == "$lt") {
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primop = "lt";
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always_uint = true;
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}
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if (cell->type == "$le") {
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else if (cell->type == "$le") {
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primop = "leq";
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always_uint = true;
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}
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if ((cell->type == "$shl") | (cell->type == "$sshl")) primop = "dshl";
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if ((cell->type == "$shr") | (cell->type == "$sshr")) primop = "dshr";
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if ((cell->type == "$logic_and")) {
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else if ((cell->type == "$shl") | (cell->type == "$sshl")) {
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// FIRRTL will widen the result (y) by the amount of the shift.
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// We'll need to offset this by extracting the un-widened portion as Verilog would do.
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extract_y_bits = true;
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// Is the shift amount constant?
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auto b_sig = cell->getPort("\\B");
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if (b_sig.is_fully_const()) {
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primop = "shl";
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} else {
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primop = "dshl";
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// Convert from FIRRTL left shift semantics.
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b_expr = gen_dshl(b_expr, b_padded_width);
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}
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}
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else if ((cell->type == "$shr") | (cell->type == "$sshr")) {
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// We don't need to extract a specific range of bits.
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extract_y_bits = false;
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// Is the shift amount constant?
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auto b_sig = cell->getPort("\\B");
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if (b_sig.is_fully_const()) {
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primop = "shr";
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} else {
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primop = "dshr";
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}
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}
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else if ((cell->type == "$logic_and")) {
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primop = "and";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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}
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if ((cell->type == "$logic_or")) {
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else if ((cell->type == "$logic_or")) {
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primop = "or";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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@ -388,6 +485,11 @@ struct FirrtlWorker
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string expr = stringf("%s(%s, %s)", primop.c_str(), a_expr.c_str(), b_expr.c_str());
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// Deal with FIRRTL's "shift widens" semantics
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if (extract_y_bits) {
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expr = stringf("bits(%s, %d, 0)", expr.c_str(), y_width - 1);
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}
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if ((is_signed && !always_uint) || cell->type.in("$sub"))
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expr = stringf("asUInt(%s)", expr.c_str());
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@ -513,7 +615,67 @@ struct FirrtlWorker
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continue;
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}
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log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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// This may be a parameterized module - paramod.
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if (cell->type.substr(0, 8) == "$paramod")
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{
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auto paramod_module = log_id(module);
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auto paramod_instance = log_id(cell);
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process_instance(cell, wire_exprs);
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continue;
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}
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if (cell->type == "$shiftx") {
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// assign y = a[b +: y_width];
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// We'll extract the correct bits as part of the primop.
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string y_id = make_id(cell->name);
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int y_width = cell->parameters.at("\\Y_WIDTH").as_int();
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string a_expr = make_expr(cell->getPort("\\A"));
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// Get the initial bit selector
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string b_expr = make_expr(cell->getPort("\\B"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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if (cell->getParam("\\B_SIGNED").as_bool()) {
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// Use validif to constrain the selection (test the sign bit)
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auto b_string = b_expr.c_str();
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int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1;
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b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
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}
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string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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}
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if (cell->type == "$shift") {
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// assign y = a >> b;
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// where b may be negative
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string y_id = make_id(cell->name);
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int y_width = cell->parameters.at("\\Y_WIDTH").as_int();
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string a_expr = make_expr(cell->getPort("\\A"));
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string b_expr = make_expr(cell->getPort("\\B"));
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auto b_string = b_expr.c_str();
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int b_padded_width = cell->parameters.at("\\B_WIDTH").as_int();
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string expr;
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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if (cell->getParam("\\B_SIGNED").as_bool()) {
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// We generate a left or right shift based on the sign of b.
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std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_padded_width).c_str(), y_width);
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std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
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expr = stringf("mux(%s < 0, %s, %s)",
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b_string,
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dshl.c_str(),
|
||||
dshr.c_str()
|
||||
);
|
||||
} else {
|
||||
expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
|
||||
}
|
||||
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
|
||||
register_reverse_wire_map(y_id, cell->getPort("\\Y"));
|
||||
continue;
|
||||
}
|
||||
log_warning("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
|
||||
}
|
||||
|
||||
for (auto conn : module->connections())
|
||||
|
|
@ -629,38 +791,53 @@ struct FirrtlBackend : public Backend {
|
|||
log(" write_firrtl [options] [filename]\n");
|
||||
log("\n");
|
||||
log("Write a FIRRTL netlist of the current design.\n");
|
||||
log("The following commands are executed by this command:\n");
|
||||
log(" pmuxtree\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
// if (args[argidx] == "-aig") {
|
||||
// aig_mode = true;
|
||||
// continue;
|
||||
// }
|
||||
break;
|
||||
size_t argidx = args.size(); // We aren't expecting any arguments.
|
||||
|
||||
// If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
|
||||
if (filename == "") {
|
||||
if (argidx > 0 && args[argidx - 1][0] != '-') {
|
||||
// extra_args and friends need to see this argument.
|
||||
argidx -= 1;
|
||||
filename = args[argidx];
|
||||
}
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
||||
log_header(design, "Executing FIRRTL backend.\n");
|
||||
log_push();
|
||||
|
||||
Module *top = design->top_module();
|
||||
|
||||
if (top == nullptr)
|
||||
log_error("No top module found!\n");
|
||||
Pass::call(design, stringf("pmuxtree"));
|
||||
|
||||
namecache.clear();
|
||||
autoid_counter = 0;
|
||||
|
||||
// Get the top module, or a reasonable facsimile - we need something for the circuit name.
|
||||
Module *top = design->top_module();
|
||||
Module *last = nullptr;
|
||||
// Generate module and wire names.
|
||||
for (auto module : design->modules()) {
|
||||
make_id(module->name);
|
||||
last = module;
|
||||
if (top == nullptr && module->get_bool_attribute("\\top")) {
|
||||
top = module;
|
||||
}
|
||||
for (auto wire : module->wires())
|
||||
if (wire->port_id)
|
||||
make_id(wire->name);
|
||||
}
|
||||
|
||||
if (top == nullptr)
|
||||
top = last;
|
||||
|
||||
*f << stringf("circuit %s:\n", make_id(top->name));
|
||||
|
||||
for (auto module : design->modules())
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
|
||||
code_hdl_models_arbiter.v error: reg rst; cannot be driven by primitives or continuous assignment.
|
||||
code_hdl_models_clk_div_45.v yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
|
||||
code_hdl_models_d_ff_gates.v combinational loop
|
||||
code_hdl_models_d_latch_gates.v combinational loop
|
||||
code_hdl_models_dff_async_reset.v $adff
|
||||
code_hdl_models_tff_async_reset.v $adff
|
||||
code_hdl_models_uart.v $adff
|
||||
code_specman_switch_fabric.v subfield assignment (bits() <= ...)
|
||||
code_tidbits_asyn_reset.v $adff
|
||||
code_tidbits_reg_seq_example.v $adff
|
||||
code_verilog_tutorial_always_example.v empty module
|
||||
code_verilog_tutorial_escape_id.v make_id issues (name begins with a digit)
|
||||
code_verilog_tutorial_explicit.v firrtl backend bug (empty module)
|
||||
code_verilog_tutorial_first_counter.v error: reg rst; cannot be driven by primitives or continuous assignment.
|
||||
code_verilog_tutorial_fsm_full.v error: reg reset; cannot be driven by primitives or continuous assignment.
|
||||
code_verilog_tutorial_if_else.v empty module (everything is under 'always @ (posedge clk)')
|
||||
[code_verilog_tutorial_n_out_primitive.v empty module
|
||||
code_verilog_tutorial_parallel_if.v empty module (everything is under 'always @ (posedge clk)')
|
||||
code_verilog_tutorial_simple_function.v empty module (no hardware)
|
||||
code_verilog_tutorial_simple_if.v empty module (everything is under 'always @ (posedge clk)')
|
||||
code_verilog_tutorial_task_global.v empty module (everything is under 'always @ (posedge clk)')
|
||||
code_verilog_tutorial_v2k_reg.v empty module
|
||||
code_verilog_tutorial_which_clock.v $adff
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
|
||||
arraycells.v inst id[0] of
|
||||
dff_different_styles.v
|
||||
generate.v combinational loop
|
||||
hierdefparam.v inst id[0] of
|
||||
i2c_master_tests.v $adff
|
||||
macros.v drops modules
|
||||
mem2reg.v drops modules
|
||||
mem_arst.v $adff
|
||||
memory.v $adff
|
||||
multiplier.v inst id[0] of
|
||||
muxtree.v drops modules
|
||||
omsp_dbg_uart.v $adff
|
||||
operators.v $pow
|
||||
paramods.v subfield assignment (bits() <= ...)
|
||||
partsel.v drops modules
|
||||
process.v drops modules
|
||||
realexpr.v drops modules
|
||||
scopes.v original verilog issues ( -x where x isn't declared signed)
|
||||
sincos.v $adff
|
||||
specify.v no code (empty module generates error
|
||||
subbytes.v $adff
|
||||
task_func.v drops modules
|
||||
values.v combinational loop
|
||||
vloghammer.v combinational loop
|
||||
wreduce.v original verilog issues ( -x where x isn't declared signed)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
EXTRA_FLAGS=
|
||||
SEED=
|
||||
|
||||
# Don't bother defining default values for SEED and EXTRA_FLAGS.
|
||||
# Their "natural" default values should be sufficient,
|
||||
# and they may be overridden in the environment.
|
||||
ifneq ($(strip $(SEED)),)
|
||||
SEEDOPT=-S$(SEED)
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -17,12 +17,18 @@ scriptfiles=""
|
|||
scriptopt=""
|
||||
toolsdir="$(cd $(dirname $0); pwd)"
|
||||
warn_iverilog_git=false
|
||||
# The following are used in verilog to firrtl regression tests.
|
||||
# Typically these will be passed as environment variables:
|
||||
#EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
|
||||
# The tests are skipped if firrtl2verilog is the empty string (the default).
|
||||
firrtl2verilog=""
|
||||
xfirrtl="../xfirrtl"
|
||||
|
||||
if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
|
||||
( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
|
||||
fi
|
||||
|
||||
while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
|
||||
while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
|
||||
case "$opt" in
|
||||
x)
|
||||
use_xsim=true ;;
|
||||
|
|
@ -59,8 +65,24 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
|
|||
include_opts="$include_opts -I $OPTARG"
|
||||
xinclude_opts="$xinclude_opts -i $OPTARG"
|
||||
minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
|
||||
-)
|
||||
case "${OPTARG}" in
|
||||
xfirrtl)
|
||||
xfirrtl="${!OPTIND}"
|
||||
OPTIND=$(( $OPTIND + 1 ))
|
||||
;;
|
||||
firrtl2verilog)
|
||||
firrtl2verilog="${!OPTIND}"
|
||||
OPTIND=$(( $OPTIND + 1 ))
|
||||
;;
|
||||
*)
|
||||
if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
|
||||
echo "Unknown option --${OPTARG}" >&2
|
||||
fi
|
||||
;;
|
||||
esac;;
|
||||
*)
|
||||
echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
|
||||
echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
|
||||
exit 1
|
||||
esac
|
||||
done
|
||||
|
|
@ -109,6 +131,8 @@ do
|
|||
fn=$(basename $fn)
|
||||
bn=$(basename $bn)
|
||||
|
||||
rm -f ${bn}_ref.fir
|
||||
|
||||
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
|
||||
|
||||
if [ ! -f ../${bn}_tb.v ]; then
|
||||
|
|
@ -148,6 +172,13 @@ do
|
|||
else
|
||||
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
|
||||
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
|
||||
if [ -n "$firrtl2verilog" ]; then
|
||||
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
|
||||
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
|
||||
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v -X verilog
|
||||
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
|
||||
fi
|
||||
fi
|
||||
fi
|
||||
touch ../${bn}.log
|
||||
}
|
||||
|
|
@ -160,14 +191,18 @@ do
|
|||
( set -ex; body; ) > ${bn}.err 2>&1
|
||||
fi
|
||||
|
||||
did_firrtl=""
|
||||
if [ -f ${bn}.out/${bn}_ref.fir ]; then
|
||||
did_firrtl="+FIRRTL "
|
||||
fi
|
||||
if [ -f ${bn}.log ]; then
|
||||
mv ${bn}.err ${bn}.log
|
||||
echo "${status_prefix}-> ok"
|
||||
echo "${status_prefix}${did_firrtl}-> ok"
|
||||
elif [ -f ${bn}.skip ]; then
|
||||
mv ${bn}.err ${bn}.skip
|
||||
echo "${status_prefix}-> skip"
|
||||
else
|
||||
echo "${status_prefix}-> ERROR!"
|
||||
echo "${status_prefix}${did_firrtl}-> ERROR!"
|
||||
if $warn_iverilog_git; then
|
||||
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
|
||||
fi
|
||||
|
|
|
|||
Loading…
Reference in New Issue