mirror of https://github.com/YosysHQ/yosys.git
Added smtc "final" statement
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7500b403de
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adcda6817e
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@ -121,6 +121,7 @@ if tempind and len(inconstr) != 0:
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sys.exit(1)
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constr_final_start = None
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constr_asserts = defaultdict(list)
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constr_assumes = defaultdict(list)
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@ -142,6 +143,21 @@ for fn in inconstr:
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current_states.add(0)
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continue
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if tokens[0] == "final":
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constr_final = True
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if len(tokens) == 1:
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current_states = set(["final-%d" % i for i in range(0, num_steps+1)])
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constr_final_start = 0
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elif len(tokens) == 2:
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i = int(tokens[1])
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assert i < 0
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current_states = set(["final-%d" % i for i in range(-i, num_steps+1)])
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constr_final_start = -i if constr_final_start is None else min(constr_final_start, -i)
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else:
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assert 0
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continue
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continue
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if tokens[0] == "state":
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current_states = set()
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for token in tokens[1:]:
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@ -190,9 +206,13 @@ for fn in inconstr:
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assert 0
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def get_constr_expr(db, state):
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if state not in db:
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return "true"
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def get_constr_expr(db, state, final=False):
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if final:
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if ("final-%d" % state) not in db:
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return "true"
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else:
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if state not in db:
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return "true"
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netref_regex = re.compile(r'(^|[( ])\[(-?[0-9]+:|)([^\]]+)\](?=[ )]|$)')
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@ -211,7 +231,7 @@ def get_constr_expr(db, state):
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return match.group(1) + expr
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expr_list = list()
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for expr in db[state]:
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for expr in db[("final-%d" % state) if final else state]:
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expr = netref_regex.sub(replace_netref, expr)
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expr_list.append(expr)
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@ -530,9 +550,32 @@ else: # not tempind
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smt.write("(pop 1)")
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for i in range(step, last_check_step+1):
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smt.write("(assert (%s_a s%d))" % (topmod, i))
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smt.write("(assert %s)" % get_constr_expr(constr_asserts, i))
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if constr_final_start is not None:
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for i in range(step, last_check_step+1):
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if i < constr_final_start:
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continue
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print("%s Checking final constraints in step %d.." % (smt.timestamp(), i))
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smt.write("(push 1)")
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smt.write("(assert %s)" % get_constr_expr(constr_assumes, i, final=True))
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smt.write("(assert (not %s))" % get_constr_expr(constr_asserts, i, final=True))
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if smt.check_sat() == "sat":
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print("%s BMC failed!" % smt.timestamp())
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print_failed_asserts(topmod, "s%d" % i, topmod)
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write_trace(i)
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retstatus = False
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break
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smt.write("(pop 1)")
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if not retstatus:
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break
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if constr_final_start is None:
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for i in range(step, last_check_step+1):
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smt.write("(assert (%s_a s%d))" % (topmod, i))
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smt.write("(assert %s)" % get_constr_expr(constr_asserts, i))
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if gentrace:
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print("%s Solving for step %d.." % (smt.timestamp(), step))
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@ -10,3 +10,6 @@ demo2_tb.vcd
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demo3.smt2
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demo3.vcd
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demo3.yslog
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demo4.smt2
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demo4.vcd
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demo4.yslog
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@ -1,5 +1,5 @@
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all: demo1 demo2 demo3
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all: demo1 demo2 demo3 demo4
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demo1: demo1.smt2
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yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
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@ -13,6 +13,9 @@ demo2: demo2.smt2
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demo3: demo3.smt2
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yosys-smtbmc --dump-vcd demo3.vcd --smtc demo3.smtc demo3.smt2
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demo4: demo4.smt2
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yosys-smtbmc -s yices --dump-vcd demo4.vcd --smtc demo4.smtc demo4.smt2
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demo1.smt2: demo1.v
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yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires -mem -bv demo1.smt2'
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@ -22,10 +25,14 @@ demo2.smt2: demo2.v
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demo3.smt2: demo3.v
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yosys -ql demo3.yslog -p 'read_verilog -formal demo3.v; prep -top demo3 -nordff; write_smt2 -wires -mem -bv demo3.smt2'
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demo4.smt2: demo4.v
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yosys -ql demo4.yslog -p 'read_verilog -formal demo4.v; prep -top demo4 -nordff; write_smt2 -wires -mem -bv demo4.smt2'
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clean:
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rm -f demo1.yslog demo1.smt2 demo1.vcd
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rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
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rm -f demo3.yslog demo3.smt2 demo3.vcd
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rm -f demo4.yslog demo4.smt2 demo4.vcd
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.PHONY: demo1 demo2 demo3 clean
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.PHONY: demo1 demo2 demo3 demo4 clean
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@ -0,0 +1,11 @@
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initial
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assume [rst]
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always -1
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assume (not [rst])
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assume (=> [-1:inv2] [inv2])
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final -2
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assume [-1:inv2]
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assume (not [-2:inv2])
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assert (= [r1] [r2])
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@ -0,0 +1,13 @@
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// Demo for "final" smtc constraints
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module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2);
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always @(posedge clk) begin
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if (rst) begin
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r1 <= in;
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r2 <= -in;
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end else begin
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r1 <= r1 + in;
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r2 <= inv2 ? -(r2 - in) : (r2 - in);
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end
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end
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endmodule
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