mirror of https://github.com/YosysHQ/yosys.git
Add SMT2 statebv mode (inactive for now)
This commit is contained in:
Clifford Wolf
parent
f648b7cf79
commit
a9c3acf5a2
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@ -32,8 +32,8 @@ struct Smt2Worker
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CellTypes ct;
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SigMap sigmap;
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RTLIL::Module *module;
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bool bvmode, memmode, wiresmode, verbose;
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int idcounter;
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bool bvmode, memmode, wiresmode, verbose, statebv;
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int idcounter, statebv_width;
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std::vector<std::string> decls, trans, hier;
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std::map<RTLIL::SigBit, RTLIL::Cell*> bit_driver;
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@ -63,12 +63,41 @@ struct Smt2Worker
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return get_id(obj->name);
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}
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void makebits(std::string name, int width = 0, std::string comment = std::string())
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{
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std::string decl_str;
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if (statebv)
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{
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if (width == 0) {
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decl_str = stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name.c_str(), get_id(module), statebv_width, statebv_width);
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statebv_width += 1;
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} else {
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decl_str = stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name.c_str(), get_id(module), width, statebv_width+width-1, statebv_width);
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statebv_width += width;
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}
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}
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else
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{
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if (width == 0) {
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decl_str = stringf("(declare-fun |%s| (|%s_s|) Bool)\n", name.c_str(), get_id(module));
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} else {
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decl_str = stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name.c_str(), get_id(module), width);
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}
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}
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if (!comment.empty())
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decl_str += " ; " + comment;
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decls.push_back(decl_str + "\n");
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}
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Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose) :
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ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode),
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wiresmode(wiresmode), verbose(verbose), idcounter(0)
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{
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decls.push_back(stringf("(declare-sort |%s_s| 0)\n", get_id(module)));
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decls.push_back(stringf("(declare-fun |%s_is| (|%s_s|) Bool)\n", get_id(module), get_id(module)));
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statebv_width = 0;
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statebv = bvmode && !memmode && false; // FIXME
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makebits(stringf("%s_is", get_id(module)));
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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@ -162,8 +191,7 @@ struct Smt2Worker
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if (fcache.count(bit) == 0) {
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if (verbose) log("%*s-> external bool: %s\n", 2+2*GetSize(recursive_cells), "",
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log_signal(bit));
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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get_id(module), idcounter, get_id(module), log_signal(bit)));
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makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(bit));
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register_bool(bit, idcounter++);
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}
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@ -237,8 +265,7 @@ struct Smt2Worker
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log_signal(sig.extract(i, j)));
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for (auto bit : sig.extract(i, j))
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log_assert(bit_driver.count(bit) == 0);
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
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get_id(module), idcounter, get_id(module), j, log_signal(sig.extract(i, j))));
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makebits(stringf("%s#%d", get_id(module), idcounter), j, log_signal(sig.extract(i, j)));
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subexpr.push_back(stringf("(|%s#%d| %s)", get_id(module), idcounter, state_name));
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register_bv(sig.extract(i, j), idcounter++);
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}
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@ -382,8 +409,7 @@ struct Smt2Worker
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if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
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{
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registers.insert(cell);
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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get_id(module), idcounter, get_id(module), log_signal(cell->getPort("\\Q"))));
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makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort("\\Q")));
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register_bool(cell->getPort("\\Q"), idcounter++);
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recursive_cells.erase(cell);
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return;
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@ -410,8 +436,7 @@ struct Smt2Worker
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if (cell->type.in("$ff", "$dff"))
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{
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registers.insert(cell);
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
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get_id(module), idcounter, get_id(module), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))));
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makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q")));
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register_bv(cell->getPort("\\Q"), idcounter++);
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recursive_cells.erase(cell);
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return;
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@ -422,8 +447,7 @@ struct Smt2Worker
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registers.insert(cell);
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decls.push_back(stringf("; yosys-smt2-%s %s#%d %s\n", cell->type.c_str() + 1, get_id(module), idcounter,
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cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell)));
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
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get_id(module), idcounter, get_id(module), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y"))));
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makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y")));
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register_bv(cell->getPort("\\Y"), idcounter++);
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recursive_cells.erase(cell);
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return;
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@ -559,24 +583,22 @@ struct Smt2Worker
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if (w->port_output && !w->port_input) {
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if (GetSize(w) > 1) {
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if (bvmode) {
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
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get_id(module), idcounter, get_id(module), GetSize(w), log_signal(sig)));
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makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(w), log_signal(sig));
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register_bv(sig, idcounter++);
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} else {
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for (int i = 0; i < GetSize(w); i++) {
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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get_id(module), idcounter, get_id(module), log_signal(sig[i])));
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makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(sig[i]));
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register_bool(sig[i], idcounter++);
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}
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}
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} else {
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decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
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get_id(module), idcounter, get_id(module), log_signal(sig)));
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makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(sig));
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register_bool(sig, idcounter++);
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}
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}
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}
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// FIXME (statebv)
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decls.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
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get_id(module), get_id(cell->name), get_id(module), get_id(cell->type)));
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@ -854,6 +876,11 @@ struct Smt2Worker
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{
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f << stringf("; yosys-smt2-module %s\n", get_id(module));
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if (statebv)
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f << stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module), statebv_width);
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else
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f << stringf("(declare-sort |%s_s| 0)\n", get_id(module));
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for (auto it : decls)
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f << it;
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