mirror of https://github.com/YosysHQ/yosys.git
Added EDIF backend support for multi-bit cell ports
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1b159bc955
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@ -111,7 +111,7 @@ struct EdifBackend : public Backend {
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log_header("Executing EDIF backend.\n");
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std::string top_module_name;
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std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
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std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
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CellTypes ct(design);
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EdifNames edif_names;
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@ -150,12 +150,8 @@ struct EdifBackend : public Backend {
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RTLIL::Cell *cell = cell_it.second;
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if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
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lib_cell_ports[cell->type];
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for (auto p : cell->connections()) {
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if (p.second.size() > 1)
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log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
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RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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lib_cell_ports[cell->type].insert(p.first);
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}
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for (auto p : cell->connections())
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lib_cell_ports[cell->type][p.first] = GetSize(p.second);
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}
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}
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}
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@ -198,12 +194,15 @@ struct EdifBackend : public Backend {
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for (auto &port_it : cell_it.second) {
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const char *dir = "INOUT";
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if (ct.cell_known(cell_it.first)) {
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if (!ct.cell_output(cell_it.first, port_it))
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if (!ct.cell_output(cell_it.first, port_it.first))
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dir = "INPUT";
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else if (!ct.cell_input(cell_it.first, port_it))
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else if (!ct.cell_input(cell_it.first, port_it.first))
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dir = "OUTPUT";
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}
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*f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it), dir);
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if (port_it.second == 1)
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*f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
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else
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*f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(port_it.first), port_it.second, dir);
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}
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*f << stringf(" )\n");
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*f << stringf(" )\n");
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@ -303,7 +302,7 @@ struct EdifBackend : public Backend {
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char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
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hex_string = std::string(digit_str) + hex_string;
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}
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*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str());
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*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
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}
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*f << stringf(")\n");
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for (auto &p : cell->connections()) {
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