mirror of https://github.com/YosysHQ/yosys.git
Fixed instantiating multi-bit ports in edif backend
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3c5e973092
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@ -303,8 +303,10 @@ struct EdifBackend : public Backend {
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sig.expand();
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for (int i = 0; i < sig.width; i++) {
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RTLIL::SigSpec sigbit(sig.chunks.at(i));
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std::string portname = sig.width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(p.first), i) : RTLIL::id2cstr(p.first);
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net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(portname).c_str(), EDIF_NAME(cell->name)));
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if (sig.width == 1)
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net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), EDIF_NAME(cell->name)));
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else
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net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), i, EDIF_NAME(cell->name)));
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}
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}
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}
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