mirror of https://github.com/YosysHQ/yosys.git
Add array support to btor back-end
This commit is contained in:
Clifford Wolf
parent
ad901671c5
commit
30f23281ed
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@ -102,6 +102,19 @@ struct BtorWorker
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return sorts_bv.at(width);
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}
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int get_mem_sid(int abits, int dbits)
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{
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pair<int, int> key(abits, dbits);
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if (sorts_mem.count(key) == 0) {
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int addr_sid = get_bv_sid(abits);
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int data_sid = get_bv_sid(dbits);
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int nid = next_nid++;
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btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
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sorts_mem[key] = nid;
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}
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return sorts_mem.at(key);
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}
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void add_nid_sig(int nid, const SigSpec &sig)
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{
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if (verbose)
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@ -558,6 +571,103 @@ struct BtorWorker
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goto okay;
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}
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if (cell->type == "$mem")
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{
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int abits = cell->getParam("\\ABITS").as_int();
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int width = cell->getParam("\\WIDTH").as_int();
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int rdports = cell->getParam("\\RD_PORTS").as_int();
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int wrports = cell->getParam("\\WR_PORTS").as_int();
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Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
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Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
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bool asyncwr = wr_clk_en.is_fully_zero();
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if (!asyncwr && !wr_clk_en.is_fully_ones())
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log_error("Memory %s.%s has mixed async/sync write ports.\n",
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log_id(module), log_id(cell));
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if (!rd_clk_en.is_fully_zero())
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log_error("Memory %s.%s has sync read ports.\n",
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log_id(module), log_id(cell));
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SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
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SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
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SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
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SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
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SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
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int data_sid = get_bv_sid(width);
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int sid = get_mem_sid(abits, width);
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int nid = next_nid++;
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int nid_head = nid;
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if (cell->name[0] == '$')
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btorf("%d state %d\n", nid, sid);
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else
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btorf("%d state %d %s\n", nid, sid, log_id(cell));
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if (asyncwr)
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{
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for (int port = 0; port < wrports; port++)
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{
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SigSpec wa = sig_wr_addr.extract(port*abits, abits);
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SigSpec wd = sig_wr_data.extract(port*width, width);
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SigSpec we = sig_wr_en.extract(port*width, width);
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int wa_nid = get_sig_nid(wa);
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int wd_nid = get_sig_nid(wd);
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int we_nid = get_sig_nid(we);
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int nid2 = next_nid++;
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btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
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int nid3 = next_nid++;
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btorf("%d not %d %d %d\n", nid3, data_sid, we_nid);
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int nid4 = next_nid++;
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btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
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int nid5 = next_nid++;
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btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
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int nid6 = next_nid++;
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btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
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int nid7 = next_nid++;
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btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
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nid_head = nid7;
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}
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}
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for (int port = 0; port < rdports; port++)
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{
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SigSpec ra = sig_rd_addr.extract(port*abits, abits);
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SigSpec rd = sig_rd_data.extract(port*width, width);
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int ra_nid = get_sig_nid(ra);
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int rd_nid = next_nid++;
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btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);
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add_nid_sig(rd_nid, rd);
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}
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if (!asyncwr)
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{
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ff_todo.push_back(make_pair(nid, cell));
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}
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else
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{
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int nid2 = next_nid++;
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btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
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}
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goto okay;
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}
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log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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okay:
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@ -851,15 +961,68 @@ struct BtorWorker
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for (auto &it : todo)
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{
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btorf_push(stringf("next %s", log_id(it.second)));
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int nid = it.first;
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Cell *cell = it.second;
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SigSpec sig = sigmap(it.second->getPort("\\D"));
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btorf_push(stringf("next %s", log_id(cell)));
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int nid = get_sig_nid(sig);
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int sid = get_bv_sid(GetSize(sig));
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btorf("%d next %d %d %d\n", next_nid++, sid, it.first, nid);
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if (cell->type == "$mem")
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{
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int abits = cell->getParam("\\ABITS").as_int();
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int width = cell->getParam("\\WIDTH").as_int();
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int wrports = cell->getParam("\\WR_PORTS").as_int();
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btorf_pop(stringf("next %s", log_id(it.second)));
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SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
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SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
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SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
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int data_sid = get_bv_sid(width);
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int sid = get_mem_sid(abits, width);
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int nid_head = nid;
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for (int port = 0; port < wrports; port++)
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{
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SigSpec wa = sig_wr_addr.extract(port*abits, abits);
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SigSpec wd = sig_wr_data.extract(port*width, width);
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SigSpec we = sig_wr_en.extract(port*width, width);
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int wa_nid = get_sig_nid(wa);
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int wd_nid = get_sig_nid(wd);
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int we_nid = get_sig_nid(we);
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int nid2 = next_nid++;
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btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);
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int nid3 = next_nid++;
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btorf("%d not %d %d %d\n", nid3, data_sid, we_nid);
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int nid4 = next_nid++;
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btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);
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int nid5 = next_nid++;
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btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);
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int nid6 = next_nid++;
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btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);
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int nid7 = next_nid++;
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btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);
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nid_head = nid7;
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}
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int nid2 = next_nid++;
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btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
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}
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else
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{
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SigSpec sig = sigmap(cell->getPort("\\D"));
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int nid_q = get_sig_nid(sig);
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int sid = get_bv_sid(GetSize(sig));
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btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q);
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}
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btorf_pop(stringf("next %s", log_id(cell)));
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}
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}
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