mirror of https://github.com/YosysHQ/yosys.git
Improvements in yosys-smtbmc
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1d83854d84
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302166dd59
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@ -631,6 +631,7 @@ struct Smt2Worker
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for (auto it : decls)
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f << it;
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f << stringf("; yosys-smt2-module %s\n", log_id(module));
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f << stringf("(define-fun |%s_t| ((state |%s_s|) (next_state |%s_s|)) Bool ", log_id(module), log_id(module), log_id(module));
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if (GetSize(trans) > 1) {
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f << "(and\n";
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@ -26,7 +26,7 @@ num_steps = 20
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vcdfile = None
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tempind = False
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assume_skipped = None
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topmod = "main"
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topmod = None
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so = smtopts()
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@ -49,7 +49,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
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instead of BMC run temporal induction
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-m <module_name>
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name of the top module, default: main
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name of the top module
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""" + so.helpmsg())
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sys.exit(1)
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@ -97,8 +97,12 @@ with open(args[0], "r") as f:
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match = debug_nets_re.match(line)
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if match:
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debug_nets.add(match.group(2))
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if line.startswith("; yosys-smt2-module") and topmod is None:
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topmod = line.split()[2]
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smt.write(line)
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assert topmod is not None
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def write_vcd_model(steps):
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print("%s Writing model to VCD file." % smt.timestamp())
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@ -313,6 +313,7 @@ class mkvcd:
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assert t >= self.t
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if t != self.t:
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if self.t == -1:
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print("$var event 1 ! smt_clock $end", file=self.f)
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for name in sorted(self.nets):
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key, width = self.nets[name]
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print("$var wire %d %s %s $end" % (width, key, name), file=self.f)
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@ -320,4 +321,5 @@ class mkvcd:
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self.t = t
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assert self.t >= 0
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print("#%d" % self.t, file=self.f)
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print("1!", file=self.f)
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