mirror of https://github.com/YosysHQ/yosys.git
Encode large (>32 bits) parameters as hex string in edif backend
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2feee7415d
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09e200797a
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@ -216,10 +216,23 @@ struct EdifBackend : public Backend {
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fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type),
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lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
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for (auto &p : cell->parameters)
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if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
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if (!p.second.str.empty())
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fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.str.c_str());
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else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
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fprintf(f, "\n (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int());
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else
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fprintf(f, "\n (property %s FIXME)", EDIF_NAME(p.first));
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else {
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std::string hex_string = "";
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for (size_t i = 0; i < p.second.bits.size(); i += 4) {
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int digit_value = 0;
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if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value += 1;
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if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value += 2;
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if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value += 3;
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if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value += 4;
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char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
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hex_string = std::string(digit_str) + hex_string;
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}
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fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), hex_string.c_str());
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}
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fprintf(f, ")\n");
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for (auto &p : cell->connections) {
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RTLIL::SigSpec sig = sigmap(p.second);
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