mirror of https://github.com/YosysHQ/yosys.git
Fix bug in write_smt2 (export logic driving hierarchical cells before exporting regs)
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d3b3dd8e88
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@ -794,6 +794,40 @@ struct Smt2Worker
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}
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}
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if (verbose) log("=> export logic driving hierarchical cells\n");
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for (auto cell : module->cells())
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if (module->design->module(cell->type) != nullptr)
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export_cell(cell);
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while (!hiercells_queue.empty())
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{
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std::set<RTLIL::Cell*> queue;
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queue.swap(hiercells_queue);
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for (auto cell : queue)
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{
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string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
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Module *m = module->design->module(cell->type);
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log_assert(m != nullptr);
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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SigSpec sig = sigmap(conn.second);
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if (bvmode || GetSize(w) == 1) {
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hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
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get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
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} else {
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for (int i = 0; i < GetSize(w); i++)
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hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
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get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
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}
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}
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}
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}
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for (int iter = 1; !registers.empty(); iter++)
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{
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pool<Cell*> this_regs;
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@ -940,40 +974,6 @@ struct Smt2Worker
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}
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}
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if (verbose) log("=> export logic driving hierarchical cells\n");
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for (auto cell : module->cells())
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if (module->design->module(cell->type) != nullptr)
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export_cell(cell);
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while (!hiercells_queue.empty())
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{
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std::set<RTLIL::Cell*> queue;
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queue.swap(hiercells_queue);
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for (auto cell : queue)
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{
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string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
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Module *m = module->design->module(cell->type);
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log_assert(m != nullptr);
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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SigSpec sig = sigmap(conn.second);
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if (bvmode || GetSize(w) == 1) {
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hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
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get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
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} else {
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for (int i = 0; i < GetSize(w); i++)
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hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
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get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
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}
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}
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}
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}
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if (verbose) log("=> finalizing SMT2 representation of %s.\n", log_id(module));
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for (auto c : hiercells) {
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