mirror of https://github.com/YosysHQ/yosys.git
Added support for $mem cells in the verilog backend.
This commit is contained in:
luke whittlesey
parent
7462618591
commit
c0b68f4848
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@ -788,8 +788,127 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == "$mem")
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{
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std::ostringstream os;
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RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
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std::string mem_id = id( cell->parameters["\\MEMID"].decode_string() );
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int abits = cell->parameters["\\ABITS"].as_int();
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int size = cell->parameters["\\SIZE"].as_int();
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int width = cell->parameters["\\WIDTH"].as_int();
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int offset = cell->parameters["\\OFFSET"].as_int();
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bool use_init = !(RTLIL::SigSpec( cell->parameters["\\INIT"] ).is_fully_undef());
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// for memory block make something like:
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// reg [7:0] memid [3:0];
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// initial begin
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// memid[0] <= ...
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// end
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int mem_val;
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RTLIL::Memory memory;
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memory.name = memid;
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memory.width = width;
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memory.start_offset = offset;
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memory.size = size;
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dump_memory(os, indent.c_str(), &memory);
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if (use_init)
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{
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os << stringf("%s" "initial begin\n", indent.c_str());
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for (int i=0; i<size; i++)
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{
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mem_val = cell->parameters["\\INIT"].extract(i*width, width).as_int();
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os << stringf("%s" " %s[%d] <= %d'd%d;\n", indent.c_str(), mem_id.c_str(), i, width, mem_val);
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}
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os << stringf("%s" "end\n", indent.c_str());
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}
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int nread_ports = cell->parameters["\\RD_PORTS"].as_int();
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RTLIL::SigSpec sig_rd_clk, sig_rd_data, sig_rd_addr;
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bool use_rd_clk, rd_clk_posedge;
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// read ports
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for (int i=0; i < nread_ports; i++)
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{
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sig_rd_clk = cell->getPort("\\RD_CLK").extract(i);
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sig_rd_data = cell->getPort("\\RD_DATA").extract(i*width, width);
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sig_rd_addr = cell->getPort("\\RD_ADDR").extract(i*abits, abits);
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use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
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rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
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if (use_rd_clk)
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{
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// for clocked read ports make something like:
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// always @(posedge clk)
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// r_data <= array_reg[r_addr];
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os << stringf("%s" "always @(%sedge ", indent.c_str(), rd_clk_posedge ? "pos" : "neg");
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dump_sigspec(os, sig_rd_clk);
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os << stringf(")\n");
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os << stringf("%s" " ", indent.c_str());
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dump_sigspec(os, sig_rd_data);
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os << stringf(" <= %s[", mem_id.c_str());
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dump_sigspec(os, sig_rd_addr);
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os << stringf("];\n");
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}else{
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// for non-clocked read-ports make something like:
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// assign r_data = array_reg[r_addr];
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os << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(os, sig_rd_data);
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os << stringf(" = %s[", mem_id.c_str());
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dump_sigspec(os, sig_rd_addr);
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os << stringf("];\n");
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}
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}
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int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int();
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RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en, sig_wr_en_bit, temp_wire;
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bool wr_clk_posedge, use_wen;
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// write ports
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for (int i=0; i < nwrite_ports; i++)
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{
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// for write-ports make something like:
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// always @(posedge clk)
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// if (wr_en)
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// memid[w_addr] <= w_data;
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sig_wr_clk = cell->getPort("\\WR_CLK").extract(i);
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sig_wr_data = cell->getPort("\\WR_DATA").extract(i*width, width);
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sig_wr_addr = cell->getPort("\\WR_ADDR").extract(i*abits, abits);
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sig_wr_en = cell->getPort("\\WR_EN").extract(i*width, width);
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sig_wr_en_bit = sig_wr_en.extract(0);
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wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool();
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use_wen = !(sig_wr_en.is_fully_const() && (sig_wr_en.as_int() == ((1 << width) - 1)));
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// if we're using wen, make sure every bit is the same wire, otherwise this verilog description won't be correct
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// question: when would WR_EN have different wires for each bit?
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if (sig_wr_en_bit.size() != 1)
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return false;
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if (use_wen)
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{
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for(int j=0; j<width; j++)
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{
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temp_wire = sig_wr_en.extract(j);
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if ( (temp_wire.size() != 1) || !(temp_wire.is_chunk() && (temp_wire.as_chunk().wire->name == sig_wr_en_bit.as_chunk().wire->name)) )
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return false;
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}
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}
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os << stringf("%s" "always @(%sedge ", indent.c_str(), wr_clk_posedge ? "pos" : "neg");
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dump_sigspec(os, sig_wr_clk);
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os << stringf(")\n");
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if (use_wen)
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{
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os << stringf("%s" " if (", indent.c_str());
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dump_sigspec(os, sig_wr_en_bit);
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os << stringf(")\n ");
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}
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os << stringf("%s" " %s[", indent.c_str(), mem_id.c_str());
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dump_sigspec(os, sig_wr_addr);
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os << stringf("] <= ");
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dump_sigspec(os, sig_wr_data);
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os << stringf(";\n");
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}
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f << os.str();
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return true;
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}
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// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
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// FIXME: $sr, $dlatch, $memrd, $memwr, $mem, $fsm
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// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
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return false;
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}
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