riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added support for $bu0 to verilog backend

This commit is contained in:
Clifford Wolf 2014-07-20 01:56:16 +02:00
parent 2278995bd8
commit 0c67393313
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
backends/verilog/verilog_backend.cc
View File

@ -581,6 +581,22 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == "$bu0")
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->connections["\\Y"]);
if (cell->parameters["\\A_SIGNED"].as_bool()) {
fprintf(f, " = $signed(");
dump_sigspec(f, cell->connections["\\A"]);
fprintf(f, ");\n");
} else {
fprintf(f, " = { 1'b0, ");
dump_sigspec(f, cell->connections["\\A"]);
fprintf(f, " };\n");
}
return true;
}
if (cell->type == "$concat")
{
fprintf(f, "%s" "assign ", indent.c_str());