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register output corrected

This commit is contained in:
Ahmed Irfan 2014-02-11 13:28:05 +01:00
parent 1a2dc48c2a
commit 1d64b3e008
1 changed files with 1 additions and 1 deletions
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2
backends/btor/btor.cc
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@ -647,7 +647,7 @@ struct BtorDumper
log(" - width is %d\n", output_width);
int cond = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1);
bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\D"));
const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
unsigned start_bit = 0;
for(unsigned i=0; i<cell_output->chunks.size(); ++i)