riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Remove check for cell->name[0] == '$'

This commit is contained in:
Eddie Hung 2019-02-06 14:53:40 -08:00
parent c373640a3a
commit 20ca795b87
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/verilog/verilog_backend.cc
View File

@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
std::string init;
if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
std::stringstream ss;
dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
init = ss.str();